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commit 4429e3d3ea38b4a5bc83f3607e247adb9128e717 Author: wangmingrong1 <[email protected]> AuthorDate: Thu Aug 21 14:56:10 2025 +0800 arch/arm64: Delete the default save for SCTLR Currently, the SCTLR register is only used to switch the thread MTE state and has no other uses. Because saving this register is special, it will take a long time after testing, so the default saving behavior is deleted. Signed-off-by: wangmingrong1 <[email protected]> --- arch/arm64/src/common/arm64_fork.c | 3 +-- arch/arm64/src/common/arm64_initialstate.c | 3 +-- arch/arm64/src/common/arm64_registerdump.c | 3 +++ arch/arm64/src/common/arm64_schedulesigaction.c | 3 +-- arch/arm64/src/common/arm64_vector_table.S | 2 ++ arch/arm64/src/common/arm64_vectors.S | 6 ++++++ 6 files changed, 14 insertions(+), 6 deletions(-) diff --git a/arch/arm64/src/common/arm64_fork.c b/arch/arm64/src/common/arm64_fork.c index 73fbd70922b..2e558a4cb90 100644 --- a/arch/arm64/src/common/arm64_fork.c +++ b/arch/arm64/src/common/arm64_fork.c @@ -225,9 +225,8 @@ pid_t arm64_fork(const struct fork_s *context) child->xcp.regs[REG_ELR] = (uint64_t)context->lr; - child->xcp.regs[REG_SCTLR_EL1] = read_sysreg(sctlr_el1); #ifdef CONFIG_ARM64_MTE - child->xcp.regs[REG_SCTLR_EL1] |= SCTLR_TCF1_BIT; + child->xcp.regs[REG_SCTLR_EL1] = read_sysreg(sctlr_el1) | SCTLR_TCF1_BIT; #endif child->xcp.regs[REG_EXE_DEPTH] = 0; diff --git a/arch/arm64/src/common/arm64_initialstate.c b/arch/arm64/src/common/arm64_initialstate.c index 91c9d1d0c7e..8ba6dcad120 100644 --- a/arch/arm64/src/common/arm64_initialstate.c +++ b/arch/arm64/src/common/arm64_initialstate.c @@ -85,9 +85,8 @@ void arm64_new_task(struct tcb_s * tcb) xcp->regs[REG_SPSR] = SPSR_MODE_EL1H; #endif - xcp->regs[REG_SCTLR_EL1] = read_sysreg(sctlr_el1); #ifdef CONFIG_ARM64_MTE - xcp->regs[REG_SCTLR_EL1] |= SCTLR_TCF1_BIT; + xcp->regs[REG_SCTLR_EL1] = read_sysreg(sctlr_el1) | SCTLR_TCF1_BIT; #endif #ifndef CONFIG_ARM64_DECODEFIQ diff --git a/arch/arm64/src/common/arm64_registerdump.c b/arch/arm64/src/common/arm64_registerdump.c index baf69cda15f..1225d353dfb 100644 --- a/arch/arm64/src/common/arm64_registerdump.c +++ b/arch/arm64/src/common/arm64_registerdump.c @@ -94,5 +94,8 @@ void up_dump_register(void *dumpregs) _alert("SP_EL0: 0x%-16"PRIx64"\n", regs[REG_SP_EL0]); _alert("SP_ELX: 0x%-16"PRIx64"\n", regs[REG_SP_ELX]); _alert("EXE_DEPTH: 0x%-16"PRIx64"\n", regs[REG_EXE_DEPTH]); + +#ifdef CONFIG_ARM64_MTE _alert("SCTLR_EL1: 0x%-16"PRIx64"\n", regs[REG_SCTLR_EL1]); +#endif } diff --git a/arch/arm64/src/common/arm64_schedulesigaction.c b/arch/arm64/src/common/arm64_schedulesigaction.c index c0b4dbc39cd..a846022394c 100644 --- a/arch/arm64/src/common/arm64_schedulesigaction.c +++ b/arch/arm64/src/common/arm64_schedulesigaction.c @@ -66,9 +66,8 @@ static void arm64_init_signal_process(struct tcb_s *tcb, uint64_t *regs) tcb->xcp.regs[REG_SPSR] = SPSR_MODE_EL1H | DAIF_FIQ_BIT | DAIF_IRQ_BIT; #endif - tcb->xcp.regs[REG_SCTLR_EL1] = read_sysreg(sctlr_el1); #ifdef CONFIG_ARM64_MTE - tcb->xcp.regs[REG_SCTLR_EL1] |= SCTLR_TCF1_BIT; + tcb->xcp.regs[REG_SCTLR_EL1] = read_sysreg(sctlr_el1) | SCTLR_TCF1_BIT; #endif #ifdef CONFIG_ARCH_KERNEL_STACK diff --git a/arch/arm64/src/common/arm64_vector_table.S b/arch/arm64/src/common/arm64_vector_table.S index a159bac2cf0..6ca66d692e3 100644 --- a/arch/arm64/src/common/arm64_vector_table.S +++ b/arch/arm64/src/common/arm64_vector_table.S @@ -269,8 +269,10 @@ SECTION_FUNC(text, arm64_exit_exception) msr spsr_el1, x1 #endif +#ifdef CONFIG_ARM64_MTE ldr x0, [sp, #8 * REG_SCTLR_EL1] msr sctlr_el1, x0 +#endif ldp x0, x1, [sp, #8 * REG_SP_EL0] msr sp_el0, x0 diff --git a/arch/arm64/src/common/arm64_vectors.S b/arch/arm64/src/common/arm64_vectors.S index d623d5f8575..eaedd7508be 100644 --- a/arch/arm64/src/common/arm64_vectors.S +++ b/arch/arm64/src/common/arm64_vectors.S @@ -84,8 +84,10 @@ SECTION_FUNC(text, up_saveusercontext) #endif stp x4, x5, [x0, #8 * REG_ELR] +#ifdef CONFIG_ARM64_MTE mrs x4, sctlr_el1 str x4, [x0, #8 * REG_SCTLR_EL1] +#endif ret @@ -119,8 +121,12 @@ SECTION_FUNC(text, arm64_jump_to_user) and x0, x0, #~SPSR_MODE_MASK #orr x0, x0, #SPSR_MODE_EL0T # EL0T=0x00, out of range for orr str x0, [sp, #8 * REG_SPSR] + +#ifdef CONFIG_ARM64_MTE mrs x0, sctlr_el1 str x0, [sp, #8 * REG_SCTLR_EL1] +#endif + b arm64_exit_exception #endif
