csanchezdll opened a new pull request, #18549: URL: https://github.com/apache/nuttx/pull/18549
Driver copied from stm32f7, which includes CEIS/SEIS clearing per reference manual. ## Summary STM32H5 MCUs have a random number generation. According to the datasheets, the whole family has it, so there is no need to make the change conditional on specific part number as other families (STM32H7, for example, do). There are two slightly different implementations of the RNG driver. One is used in plain stm32, stm32h7,and stm32f0l0g0: when error flags SEIS/CEIS are set it just reads DR again. The other is used in stm32f7 and stm32l4: it clears those flags and disables/re-enables RNG on failure. This second one is the correct procedure according to the manual, so I have made stm32h5 one used that one (copies from stm32f7). ## Impact This change will affect all STM32H5 platforms, making /dev/random appear and /dev/urandom support available for selection using Kconfig. ## Testing TBD *This section should provide a detailed description of what you did to verify your changes work and do not break existing code.* *Please provide information about your host machine, the board(s) you tested your changes on, and how you tested. Logs should be included.* *For example, when changing something in the core OS functions, you may want to run the OSTest application to verify that there are no regressions. Changes to ADC code may warrant running the `adc` example. Adding a new uORB driver may require that you run `uorb_listener` to verify correct operation.* *Pure documentation changes can just be tested with `make html` (see docs) and verification of the correct format in your browser.* **_PRs without testing information will not be accepted. We will request test logs._** -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
