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commit f47e5394b524fe01343ae3593397f268c1efe23d Author: ImBonkers <[email protected]> AuthorDate: Mon May 18 10:43:57 2026 +0200 Documentation/arm: Add STM32N6 and Nucleo-N657X0-Q Add documentation for the STMicro STM32N6 chip family and the Nucleo-N657X0-Q development board introduced in the previous two commits. - platforms/arm/stm32n6/index.rst Chip overview: core, peripherals supported in the initial port, and a pointer to the board page. - platforms/arm/stm32n6/boards/nucleo-n657x0-q/index.rst Board page, structured per Documentation/contributing/ doc_templates/board.rst: hardware summary, user LED and button pin map, the two shipped configs (nsh, ostest), and the DEV-mode flash recipe used to load NuttX into AXISRAM via ST-LINK. - platforms/arm/stm32n6/boards/nucleo-n657x0-q/nucleo-n657x0-q.jpg Photograph of the board, referenced from the board page. The pages are picked up by the existing glob-based toctree in Documentation/platforms/arm/index.rst, no parent index changes are required. Signed-off-by: ImBonkers <[email protected]> --- .../arm/stm32n6/boards/nucleo-n657x0-q/index.rst | 172 +++++++++++++++++++++ .../boards/nucleo-n657x0-q/nucleo-n657x0-q.jpg | Bin 0 -> 235978 bytes Documentation/platforms/arm/stm32n6/index.rst | 71 +++++++++ 3 files changed, 243 insertions(+) diff --git a/Documentation/platforms/arm/stm32n6/boards/nucleo-n657x0-q/index.rst b/Documentation/platforms/arm/stm32n6/boards/nucleo-n657x0-q/index.rst new file mode 100644 index 00000000000..a9eddcf134e --- /dev/null +++ b/Documentation/platforms/arm/stm32n6/boards/nucleo-n657x0-q/index.rst @@ -0,0 +1,172 @@ +================== +ST Nucleo-N657X0-Q +================== + +.. tags:: chip:stm32, chip:stm32n6, chip:stm32n657 + +.. figure:: nucleo-n657x0-q.jpg + :width: 50 % + :align: center + :alt: STMicro Nucleo-N657X0-Q development board + + Nucleo-N657X0-Q + +The STM Nucleo-N657X0-Q is a development +board for the STM32N657X0H3Q, an Arm Cortex-M55 with 4 MiB of on-chip +AXISRAM, an on-chip Neural-ART NPU, and no internal flash. In +production, code is fetched from external XSPI NOR flash and in +development, the image is loaded directly into AXISRAM by the on-board +ST-LINK-V3EC. Refer to the +https://www.st.com/en/evaluation-tools/nucleo-n657x0-q.html website +for the full product page. + +Features +======== + +* STM32N657X0H3Q MCU (Arm Cortex-M55, up to 800 MHz) +* On-chip Neural-ART NPU accelerator +* 4 MiB on-chip AXISRAM (no internal flash) +* External XSPI NOR flash interface +* On-board ST-LINK-V3EC +* 3 user LEDs (LD5 red, LD6 green, LD7 blue), plus status LEDs + (LD1 5V_PWR, LD4 PWR, LD9 COM) +* User pushbutton (B1) and reset pushbutton +* 32.768 kHz crystal oscillator +* USB Type-C connectors (ST-LINK and user) +* ST Zio connector +* ST morpho headers + +.. warning:: + + This is the initial NuttX port for the STM32N6 family. The supported + peripheral set is intentionally minimal: USART1 (the ST-LINK VCOM + console), GPIO, RCC, PWR, and the SysTick-based timer. Other on-chip + peripherals and on-board features (XSPI flash boot, networking, + user LEDs/buttons, USB, MIPI, NPU, etc) are not yet wired up. The CPU is + currently clocked at 200 MHz from PLL1. Raising it to the standard + 600 / 800 MHz operating points is deferred to a follow-up change. + +Buttons and LEDs +================ + +The board exposes three user LEDs and a user pushbutton, but the +initial NuttX port does not yet ship ``userleds`` or ``buttons`` +drivers. The hardware wiring is summarised here so a follow-up +driver can be written against an authoritative pin map: + +===== ======= ======== ====================================== +ID Color GPIO Notes +===== ======= ======== ====================================== +LD5 Red PG10 Active low +LD6 Green PG0 Active low +LD7 Blue PG8 Active low +B1 Blue PC13 Active high, external pull-down +===== ======= ======== ====================================== + +Pin Mapping +=========== + +The shipped configurations map only the pins required for the serial +console. All other GPIOs retain their reset state and are free for +application use. + +===== ============= ======= ================================= +Pin Signal AF Notes +===== ============= ======= ================================= +PE5 USART1_TX AF7 Routed to ST-LINK VCOM (host RX) +PE6 USART1_RX AF7 Routed to ST-LINK VCOM (host TX) +===== ============= ======= ================================= + +Power Supply +============ + +The board is powered over either USB Type-C connector (ST-LINK or +user) at 5 V. On-board regulators derive the MCU and I/O rails. See +the ST user manual for the full power tree and jumper selection. + +Installation +============ + +Two host tools are required: + +* A bare-metal Arm toolchain, e.g. the GNU Arm Embedded toolchain + (``arm-none-eabi-gcc``) packaged by most Linux distributions or + available from Arm. +* `STM32CubeProgrammer + <https://www.st.com/en/development-tools/stm32cubeprog.html>`_ for + loading images into AXISRAM over the on-board ST-LINK. + +Building NuttX +============== + +From the top of the NuttX source tree: + +.. code:: console + + $ ./tools/configure.sh nucleo-n657x0-q:<config> + $ make + +At the end of the build, ``nuttx.bin`` is the raw image that the +flashing step below loads into AXISRAM. + +The toolchain selection can be changed via ``make menuconfig``. + +Flashing +======== + +The board boots in development mode: the on-board ST-LINK loads the +image directly into AXISRAM at ``0x34000400`` (the first 1 KiB is +reserved for the boot ROM header) and starts execution there. Signed +XSPI flash boot via a first-stage bootloader is not yet supported. + +Use STM32CubeProgrammer's CLI to load and run ``nuttx.bin``: + +.. code:: console + + $ STM32_Programmer_CLI -c port=SWD mode=UR -halt \ + -d nuttx.bin 0x34000400 \ + -w32 0xE000ED08 0x34000400 \ + -g 0x34000400 + +The ``-w32`` write retargets VTOR to the SRAM image before the ``-g`` +jump, so the Cortex-M55 starts from the NuttX vector table rather +than the boot ROM's. + +Configurations +============== + +Each configuration is selected with:: + + $ ./tools/configure.sh nucleo-n657x0-q:<config> + +Unless otherwise noted, console output is accessed via ST-LINK +(USART1) at 115200 8N1. + +nsh +--- + +Minimal NuttShell configuration. Boots into the NSH prompt via +ST-LINK and exposes the built-in commands plus +:doc:`getprime </applications/testing/getprime/index>`-style apps +selectable via ``make menuconfig``. + +ostest +------ + +Builds the NSH configuration with :doc:`apps/testing/ostest +</applications/testing/ostest/index>` added. Run ``ostest`` from the +NSH prompt to exercise the core RTOS primitives (tasks, mutexes, +semaphores, signals, message queues, POSIX timers, condition +variables, scheduling). Used as the smoke test. + +License Exceptions +================== + +None. + +References +========== + +* [RM0486] STM32N647/657xx Arm\ :sup:`®`-based 32-bit MCUs reference manual +* [UM3417] STM32N6 Nucleo-144 board (MB1940) user manual +* [ES0620] STM32N657 errata sheet diff --git a/Documentation/platforms/arm/stm32n6/boards/nucleo-n657x0-q/nucleo-n657x0-q.jpg b/Documentation/platforms/arm/stm32n6/boards/nucleo-n657x0-q/nucleo-n657x0-q.jpg new file mode 100644 index 00000000000..9bbb4416de5 Binary files /dev/null and b/Documentation/platforms/arm/stm32n6/boards/nucleo-n657x0-q/nucleo-n657x0-q.jpg differ diff --git a/Documentation/platforms/arm/stm32n6/index.rst b/Documentation/platforms/arm/stm32n6/index.rst new file mode 100644 index 00000000000..241cca916c3 --- /dev/null +++ b/Documentation/platforms/arm/stm32n6/index.rst @@ -0,0 +1,71 @@ +========== +ST STM32N6 +========== + +This is a port of NuttX to the STM32N6 family. +The STM32N6 is a chip based on the Arm Cortex-M55. + +Development is performed on the Nucleo-N657X0-Q. At this time only the +STM32N657X0 is supported. Kconfig will need updates to support other +MCUs in the family. + +Supported MCUs +============== + +=========== ======= ================ +MCU Support Note +=========== ======= ================ +STM32N645 No +STM32N647 No +STM32N655 No +STM32N657 Yes STM32N657X0 only +=========== ======= ================ + +Peripheral Support +================== + +The following list indicates peripherals supported in NuttX: + +========== ======= =============================================== +Peripheral Support Notes +========== ======= =============================================== +GPIO Yes +PWR Yes Partial. +RCC Yes PLL1 clock tree. +USART Yes USART1 only. + +ADC No +DCACHE No +DCMIPP No +DMA No +ETH No +I2C No +ICACHE No +IWDG No +LPTIM No +LTDC No +MPU No +NPU No +RNG No +RTC No +SAI No +SDMMC No +SPI No +TIM No +USB No +XSPI No +========== ======= =============================================== + +References +========== + +[RM0486] STMicroelectronics, STM32N647/657xx Arm®-based 32-bit MCUs + +Supported Boards +================ + +.. toctree:: + :glob: + :maxdepth: 1 + + boards/*/*
