tmedicci opened a new pull request, #18931:
URL: https://github.com/apache/nuttx/pull/18931
## Summary
* arch/risc-v: Enable setting cache line size for ESP32-P4
* Enables setting the cache line size for ESP32-P4 using Kconfig options.
## Impact
Impact on user: Yes. Enable the selection of the cache line size instead of
setting a fixed value.
Impact on build: No.
Impact on hardware: No.
Impact on documentation: No.
Impact on security: No.
Impact on compatibility: No.
## Testing
This doesn't have a specific testing procedure. `ostest` can be used to
ensure that the config doesn't break anything.
### Building
```
make -j distclean
./tools/configure.sh -S esp32p4-function-ev-board:ostest
make flash ESPTOOL_PORT=/dev/ttyACM0
picocom -b 115200 /dev/ttyUSB1
```
Other cache line settings can be selected to be tested.
### Running
Just run `ostest`.
### Results
```
nsh> ostest
stdio_test: write fd=1
stdio_test: Standard I/O Check: printf
stdio_test: write fd=2
...
Final memory usage:
VARIABLE BEFORE AFTER
======== ======== ========
arena 769a0 769a0
ordblks 2 5
mxordblk 72620 6dd10
uordblks 4328 43b8
fordblks 72678 725e8
user_main: Exiting
ostest_main: Exiting with status 0
```
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