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new 280fbba5171 stm32h5/adc: Enable ADC1.OR.OP0 for INP0 and INN1.
280fbba5171 is described below
commit 280fbba5171b0e2049187a211c33b8b11cfe435d
Author: Joao Mario Lago <[email protected]>
AuthorDate: Tue Jun 23 01:21:25 2026 -0300
stm32h5/adc: Enable ADC1.OR.OP0 for INP0 and INN1.
On STM32H5, ADC1.OR.OP0 (RM0481 26.6.23) enables the GPIO switch that
routes PA0 to ADC mux (ADC1_INP0 or ADC1_INN1).
Set ADC1.OR.OP0 during `adc_setup()` when ADC1 channel 0 is selected, or
when channel 1 is configured in differential mode.
Signed-off-by: Joao Mario Lago <[email protected]>
---
arch/arm/src/stm32h5/stm32_adc.c | 38 ++++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm/src/stm32h5/stm32_adc.c b/arch/arm/src/stm32h5/stm32_adc.c
index a6036132faa..7fe90ea6464 100644
--- a/arch/arm/src/stm32h5/stm32_adc.c
+++ b/arch/arm/src/stm32h5/stm32_adc.c
@@ -203,6 +203,7 @@ static uint32_t adc_sqrbits(struct stm32_dev_s *priv, int
first,
int last, int offset);
static int adc_set_ch(struct adc_dev_s *dev, uint8_t ch);
static bool adc_internal(struct stm32_dev_s * priv, uint32_t *adc_ccr);
+static void adc_enable_optreg(struct stm32_dev_s * priv);
static void adc_startconv(struct stm32_dev_s *priv, bool enable);
#ifdef ADC_HAVE_WDG1
static void adc_wdog1_enable(struct stm32_dev_s *priv);
@@ -1481,6 +1482,8 @@ static int adc_setup(struct adc_dev_s *dev)
adc_set_ch(dev, 0);
+ adc_enable_optreg(priv);
+
/* ADC CCR configuration */
clrbits = ADC_CCR_PRESC_MASK | ADC_CCR_VREFEN |
@@ -1647,6 +1650,41 @@ static bool adc_internal(struct stm32_dev_s * priv,
uint32_t *adc_ccr)
return internal;
}
+/****************************************************************************
+ * Name: adc_enable_optreg
+ *
+ * Description:
+ * Connects ADC1_INP0/ADC1_INN1 to the ADC mux if necessary.
+ *
+ * Input Parameters:
+ * priv - A reference to the ADC block status
+ *
+ ****************************************************************************/
+
+static void adc_enable_optreg(struct stm32_dev_s * priv)
+{
+ int i;
+
+ /* ADC1.OR.OP0 (RM0481 26.6.23)
+ * Enables the GPIO switch connecting ADC1_INP0/ADC1_INN1 to the ADC mux.
+ * This bit must be set when channel ADC1_INP0 or ADCx_INN1 is selected.
+ */
+
+ if (priv->intf == 1)
+ {
+ for (i = 0; i < priv->cchannels; i++)
+ {
+ uint8_t ch = priv->chanlist[i];
+
+ if (ch == 0 || (ch == 1 && (priv->difsel & ADC_DIFSEL_CH(1))))
+ {
+ adc_putreg(priv, STM32_ADC_OR_OFFSET, ADC_OR_OP0);
+ return;
+ }
+ }
+ }
+}
+
/****************************************************************************
* Name: adc_set_ch
*
