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The following commit(s) were added to refs/heads/master by this push:
new f81705ecf53 arch/arm/src/stm32h7: Extend crypto interface to support
HW CRC32
f81705ecf53 is described below
commit f81705ecf533f9a21ce0f57859b57082d76b0f7e
Author: Peter Barada <[email protected]>
AuthorDate: Thu Jul 16 10:57:10 2026 -0400
arch/arm/src/stm32h7: Extend crypto interface to support HW CRC32
Add stm32h7 support for CRC32 HW accelerator.
Signed-off-by: Peter Barada <[email protected]>
---
arch/arm/src/stm32h7/hardware/stm32h7xxxx_crc.h | 79 +++
arch/arm/src/stm32h7/stm32_crypto.c | 556 ++++++++++++++++++++-
.../stm32h7/nucleo-h753zi/configs/crypto/defconfig | 2 +
3 files changed, 614 insertions(+), 23 deletions(-)
diff --git a/arch/arm/src/stm32h7/hardware/stm32h7xxxx_crc.h
b/arch/arm/src/stm32h7/hardware/stm32h7xxxx_crc.h
new file mode 100644
index 00000000000..149893d9e99
--- /dev/null
+++ b/arch/arm/src/stm32h7/hardware/stm32h7xxxx_crc.h
@@ -0,0 +1,79 @@
+/****************************************************************************
+ * arch/arm/src/stm32h7/hardware/stm32h7xxxx_crc.h
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7XXXX_CRC_H
+#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7XXXX_CRC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+
+#include "chip.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* CRC register offsets *****************************************************/
+
+#define STM32_CRC_DR_OFFSET 0x0000 /* Data Register */
+#define STM32_CRC_IDR_OFFSET 0x0004 /* Data Input Register */
+#define STM32_CRC_CR_OFFSET 0x0008 /* Control Register */
+#define STM32_CRC_INIT_OFFSET 0x0010 /* Init Value Register */
+#define STM32_CRC_POL_OFFSET 0x0014 /* Polynomial Register */
+
+/* CRC register addresses ***************************************************/
+
+#define STM32_CRC_DR (STM32_CRC_BASE + STM32_CRC_DR_OFFSET)
+#define STM32_CRC_IDR (STM32_CRC_BASE + STM32_CRC_IDR_OFFSET)
+#define STM32_CRC_CR (STM32_CRC_BASE + STM32_CRC_CR_OFFSET)
+#define STM32_CRC_INIT (STM32_CRC_BASE + STM32_CRC_INIT_OFFSET)
+#define STM32_CRC_POL (STM32_CRC_BASE + STM32_CRC_POL_OFFSET)
+
+/* CRC register bit definitions *********************************************/
+
+/* CRC CR register */
+
+#define CRC_CR_REVOUT_SHIFT 7
+#define CRC_CR_REV_OUT_MASK (1 << CRC_CR_REVOUT_SHIFT)
+#define CRC_CR_REV_OUT_NONE (0 << CRC_CR_REVOUT_SHIFT)
+#define CRC_CR_REV_OUT (1 << CRC_CR_REVOUT_SHIFT)
+#define CRC_CR_REV_IN_SHIFT 5
+#define CRC_CR_REV_IN_MASK (0x3 << CRC_CR_REV_IN_SHIFT)
+#define CRC_CR_REV_IN_NONE (0x0 << CRC_CR_REV_IN_SHIFT)
+#define CRC_CR_REV_IN_BYTE (0x1 << CRC_CR_REV_IN_SHIFT)
+#define CRC_CR_REV_IN_HALFWORD (0x2 << CRC_CR_REV_IN_SHIFT)
+#define CRC_CR_REV_IN_WORD (0x3 << CRC_CR_REV_IN_SHIFT)
+#define CRC_CR_POLYSIZE_SHIFT 3
+#define CRC_CR_POLYSIZE_MASK (0x3 << CRC_CR_POLYSIZE_SHIFT)
+#define CRC_CR_POLYSIZE_32BIT (0x0 << CRC_CR_POLYSIZE_SHIFT)
+#define CRC_CR_POLYSIZE_16BIT (0x1 << CRC_CR_POLYSIZE_SHIFT)
+#define CRC_CR_POLYSIZE_8BIT (0x2 << CRC_CR_POLYSIZE_SHIFT)
+#define CRC_CR_POLYSIZE_7BIT (0x3 << CRC_CR_POLYSIZE_SHIFT)
+#define CRC_CR_RESET_SHIFT 0
+#define CRC_CR_RESET (1 << CRC_CR_RESET_SHIFT)
+
+#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7XXXX_CRC_H */
diff --git a/arch/arm/src/stm32h7/stm32_crypto.c
b/arch/arm/src/stm32h7/stm32_crypto.c
index e73205f36c5..a9cc1bd9f7f 100644
--- a/arch/arm/src/stm32h7/stm32_crypto.c
+++ b/arch/arm/src/stm32h7/stm32_crypto.c
@@ -26,6 +26,7 @@
#include <nuttx/config.h>
#include <nuttx/debug.h>
+#include <sys/param.h>
#include <errno.h>
#include <stdint.h>
@@ -33,54 +34,353 @@
#include <crypto/xform.h>
#include <nuttx/crypto/crypto.h>
+#include "arm_internal.h"
+#include "hardware/stm32h7x3xx_rcc.h"
+#include "hardware/stm32h7xxxx_crc.h"
+
+/* Following constants used in reverse32() to reverse
+ * bit order of 32-bit value
+ */
+#define REV32_CONST1 0x55555555
+#define REV32_CONST2 0x33333333
+#define REV32_CONST3 0x0F0F0F0F
+#define REV32_CONST4 0x00FF00FF
+
+#define STM32H7_CRC_RESET_TIMEOUT 1000 /* should be enough loops to reset */
+#define CRC32_XOR_VALUE 0xFFFFFFFFUL
+
+#undef CONFIG_STM32_CRYPTO_DEBUG
+
+#ifdef CONFIG_STM32_CRYPTO_DEBUG
+#define stm32cryptoinfo(format, ...) \
+ do { \
+ __arch_syslog(LOG_INFO, "%s:%d " format, __FUNCTION__, __LINE__,
##__VA_ARGS__); \
+ } while (0)
+#define stm32cryptoinfo_at(func, line, format, ...) \
+ do { \
+ __arch_syslog(LOG_INFO, "%s:%d " format, func, line, ##__VA_ARGS__); \
+ } while (0)
+#define stm32crypto_getreg32(reg) stm32_crypto_getreg32(__FUNCTION__,
__LINE__, reg)
+#define stm32crypto_putreg32(val, reg) stm32_crypto_putreg32(__FUNCTION__,
__LINE__, val, reg)
+#define stm32crypto_putreg16(val, reg) stm32_crypto_putreg16(__FUNCTION__,
__LINE__, val, reg)
+#define stm32crypto_putreg8(val, reg) stm32_crypto_putreg8(__FUNCTION__,
__LINE__, val, reg)
+#else
+#define stm32cryptoinfo(format, ...)
+#define stm32cryptoinfo_at(func, line, format, ...)
+#define stm32crypto_getreg32(reg) getreg32(reg)
+#define stm32crypto_putreg32(val, reg) putreg32(val, reg)
+#define stm32crypto_putreg16(val, reg) putreg16(val, reg)
+#define stm32crypto_putreg8(val, reg) putreg8(val, reg)
+#endif
+
/****************************************************************************
* Private Data
****************************************************************************/
+static bool g_stm32_crc_initialized = false;
+
static uint32_t g_stm32_sesnum = 0;
+static FAR struct stm32_crypto_data **stm32_crypto_sessions = NULL;
+
+struct stm32_crypto_data
+{
+ int hw_alg; /* Algorithm; */
+ union
+ {
+ struct stm32_crc32
+ {
+ uint32_t init; /* init/interim CRC value */
+ } crc;
+ } u;
+ struct stm32_crypto_data *hw_next;
+};
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+bool stm32_crypto_debug_flag = true;
+
/****************************************************************************
* Private Functions
****************************************************************************/
+#ifdef CONFIG_STM32_CRYPTO_DEBUG
+struct rn
+{
+ FAR const char *name;
+ uint32_t regaddr;
+};
+
+static struct rn stm32_crypto_regnames [] =
+{
+ {
+ "RCC_AHB4RSTR",
+ STM32_RCC_AHB4RSTR,
+ },
+
+ {
+ "RCC_AHB4ENR",
+ STM32_RCC_AHB4ENR,
+ },
+
+ {
+ "CRC_DR",
+ STM32_CRC_DR,
+ },
+
+ {
+ "CRC_IDR",
+ STM32_CRC_IDR,
+ },
+
+ {
+ "CRC_CR",
+ STM32_CRC_CR,
+ },
+
+ {
+ "CRC_INIT",
+ STM32_CRC_INIT,
+ },
+
+ {
+ "CRC_POL",
+ STM32_CRC_POL,
+ },
+};
+
+const char *stm32_crypto_regname(uint32_t regaddr)
+{
+ int i;
+
+ for (i = 0; i < nitems(stm32_crypto_regnames); ++i)
+ {
+ if (stm32_crypto_regnames[i].regaddr == regaddr)
+ {
+ return stm32_crypto_regnames[i].name;
+ }
+ }
+
+ return "???";
+}
+
+static uint32_t stm32_crypto_getreg32(const char *func, int line,
+ uint32_t regaddr)
+{
+ const char *regname = stm32_crypto_regname(regaddr);
+ char buf[128];
+ uint32_t val;
+
+ val = getreg32(regaddr);
+ if (stm32_crypto_debug_flag)
+ {
+ snprintf(buf, sizeof(buf), "%08" PRIx32 "(%s)<=%08" PRIx32 "",
+ regaddr, regname, val);
+ stm32cryptoinfo_at(func, line, " %s", buf);
+ }
+
+ return val;
+}
+
+static void stm32_crypto_putreg8(const char *func, int line,
+ uint32_t val, uint32_t regaddr)
+{
+ const char *regname = stm32_crypto_regname(regaddr);
+ char buf[128];
+
+ if (stm32_crypto_debug_flag)
+ {
+ snprintf(buf, sizeof(buf), "%08" PRIx32 "(%s)=>%02" PRIx32 "",
+ regaddr, regname, (val & 0xff));
+ stm32cryptoinfo_at(func, line, " %s", buf);
+ }
+
+ putreg8(val & 0xff, regaddr);
+}
+
+static void stm32_crypto_putreg16(const char *func, int line,
+ uint32_t val, uint32_t regaddr)
+{
+ const char *regname = stm32_crypto_regname(regaddr);
+ char buf[128];
+
+ if (stm32_crypto_debug_flag)
+ {
+ snprintf(buf, sizeof(buf), "%08" PRIx32 "(%s)=>%04" PRIx32 "",
+ regaddr, regname, (val & 0xffff));
+ stm32cryptoinfo_at(func, line, " %s", buf);
+ }
+
+ putreg16(val & 0xffff, regaddr);
+}
+
+static void stm32_crypto_putreg32(const char *func, int line,
+ uint32_t val, uint32_t regaddr)
+{
+ const char *regname = stm32_crypto_regname(regaddr);
+ char buf[128];
+
+ if (stm32_crypto_debug_flag)
+ {
+ snprintf(buf, sizeof(buf), "%08" PRIx32 "(%s)=>%08" PRIx32 "",
+ regaddr, regname, val);
+ stm32cryptoinfo_at(func, line, " %s", buf);
+ }
+
+ putreg32(val, regaddr);
+}
+#endif
+
/****************************************************************************
- * Name: stm32_newsession
+ * Name: stm32_wait_for_clr
*
* Description:
- * create new session for crypto.
+ * wait for a bitmask to clear in HW register
*
****************************************************************************/
-static int stm32_newsession(uint32_t *sid, struct cryptoini *cri)
+static int stm32_wait_for_clr(uintptr_t regaddr, uint32_t bitmask,
+ uint32_t timeout)
{
- int klen;
-
- if (sid == NULL || cri == NULL)
+ uint32_t regval;
+ while (timeout--)
{
- return -EINVAL;
+ regval = stm32crypto_getreg32(regaddr);
+ if (regval & bitmask)
+ {
+ return 0;
+ }
}
- switch (cri->cri_alg)
+ return -ETIMEDOUT;
+}
+
+/****************************************************************************
+ * Name: reverse32
+ *
+ * Description:
+ * reverse bit order of 32-bit value
+ *
+ ****************************************************************************/
+
+static uint32_t reverse32(uint32_t val)
+{
+ val = ((val >> 1) & REV32_CONST1) | ((val & REV32_CONST1) << 1);
+ val = ((val >> 2) & REV32_CONST2) | ((val & REV32_CONST2) << 2);
+ val = ((val >> 4) & REV32_CONST3) | ((val & REV32_CONST3) << 4);
+ val = ((val >> 8) & REV32_CONST4) | ((val & REV32_CONST4) << 8);
+ return (val >> 16) | (val << 16);
+}
+
+static int crc32_init(struct stm32_crypto_data *sw)
+{
+ irqstate_t flags;
+ uint32_t regval;
+ int ret;
+
+ /* Set the initial value to start a CRC calculation */
+
+ sw->u.crc.init = CRC32_XOR_VALUE;
+
+ if (!g_stm32_crc_initialized)
{
- case CRYPTO_AES_CBC:
- *sid = g_stm32_sesnum++;
- break;
- case CRYPTO_AES_CTR:
- klen = cri->cri_klen / 8 - 4;
- if ((klen != 16) && (klen != 24) && (klen != 32))
- {
- /* stm32h7 aes-ctr key bits support 128, 192, or 256 */
+ g_stm32_crc_initialized = true;
- return -EINVAL;
- }
+ flags = enter_critical_section();
- *sid = g_stm32_sesnum++;
- break;
- default:
- return -EINVAL;
+ /* Clear/set AHB4RSTR to reset CRC peripheral */
+
+ regval = stm32crypto_getreg32(STM32_RCC_AHB4RSTR);
+ regval |= RCC_AHB4RSTR_CRCRST;
+ stm32crypto_putreg32(regval, STM32_RCC_AHB4RSTR);
+ regval &= ~RCC_AHB4RSTR_CRCRST;
+ stm32crypto_putreg32(regval, STM32_RCC_AHB4RSTR);
+
+ leave_critical_section(flags);
}
- return OK;
+ /* Do not set REV_OUT since that breaks being able to chain
+ * buffers by simply reading CRC_DR at end of one update and
+ * writing it back into CRC_INIT at start of next buffer
+ */
+
+ regval = stm32crypto_getreg32(STM32_CRC_CR);
+ regval &= ~(CRC_CR_REV_OUT_MASK | CRC_CR_REV_IN_MASK
+ | CRC_CR_POLYSIZE_MASK);
+ regval |= CRC_CR_POLYSIZE_32BIT;
+
+ regval |= CRC_CR_REV_IN_BYTE;
+ regval |= CRC_CR_RESET;
+
+ stm32crypto_putreg32(regval, STM32_CRC_CR);
+
+ ret = stm32_wait_for_clr(STM32_CRC_CR, CRC_CR_RESET,
+ STM32H7_CRC_RESET_TIMEOUT);
+
+ return ret;
+}
+
+static int crc32_update(struct stm32_crypto_data *sw,
+ uint8_t *buf, uint32_t len)
+{
+ const uint8_t *in_byte = buf;
+ uint32_t regval;
+
+ stm32crypto_putreg32(sw->u.crc.init, STM32_CRC_INIT);
+
+ while (len >= sizeof(uint32_t))
+ {
+ regval = (in_byte[0] << 24) | (in_byte[1] << 16)
+ | (in_byte[2] << 8) | (in_byte[3] << 0);
+ stm32crypto_putreg32(regval, STM32_CRC_DR);
+ in_byte += sizeof(uint32_t);
+ len -= sizeof(uint32_t);
+ }
+
+ if (len)
+ {
+ if (len == 1)
+ {
+ stm32crypto_putreg8(in_byte[0], STM32_CRC_DR);
+ }
+ else if (len == 2)
+ {
+ regval = ((uint16_t)(in_byte[0]) << 8) | (uint16_t)in_byte[1];
+ stm32crypto_putreg16(regval, STM32_CRC_DR);
+ }
+ else
+ {
+ regval = ((uint16_t)(in_byte[0]) << 8) | (uint16_t)in_byte[1];
+ stm32crypto_putreg16(regval, STM32_CRC_DR);
+ stm32crypto_putreg8(in_byte[2], STM32_CRC_DR);
+ }
+ }
+
+ /* Extract current CRC and save for next iteration. */
+
+ regval = stm32crypto_getreg32(STM32_CRC_DR);
+ sw->u.crc.init = regval;
+
+ return 0;
+}
+
+static int crc32_final(struct stm32_crypto_data *sw, caddr_t digest)
+{
+ uint32_t val;
+
+ /* CRC is saved in init value - but its reversed due to HW
+ * implementation. Reverse and invert to get true
+ * CRC-32 result.
+ */
+
+ val = sw->u.crc.init;
+ val = reverse32(val) ^ CRC32_XOR_VALUE;
+ stm32cryptoinfo("init: %08" PRIx32 " result: %08" PRIx32 "",
+ sw->u.crc.init, val);
+ memcpy(digest, &val, sizeof(uint32_t));
+ return 0;
}
/****************************************************************************
@@ -93,6 +393,156 @@ static int stm32_newsession(uint32_t *sid, struct
cryptoini *cri)
static int stm32_freesession(uint64_t tid)
{
+ FAR struct stm32_crypto_data *swd;
+ uint32_t sid = ((uint32_t) tid) & 0xffffffff;
+
+ if (sid > g_stm32_sesnum || stm32_crypto_sessions == NULL
+ || stm32_crypto_sessions[sid] == NULL)
+ {
+ return -EINVAL;
+ }
+
+ /* Silently accept and return */
+
+ if (sid == 0)
+ {
+ return 0;
+ }
+
+ while ((swd = stm32_crypto_sessions[sid]) != NULL)
+ {
+ stm32_crypto_sessions[sid] = swd->hw_next;
+
+ switch (swd->hw_alg)
+ {
+ case CRYPTO_CRC32:
+ case CRYPTO_AES_CBC:
+ case CRYPTO_AES_CTR:
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ kmm_free(swd);
+ }
+
+ return 0;
+}
+
+/****************************************************************************
+ * Name: stm32_newsession
+ *
+ * Description:
+ * create new session for crypto.
+ *
+ ****************************************************************************/
+
+static int stm32_newsession(uint32_t *sid, struct cryptoini *cri)
+{
+ FAR struct stm32_crypto_data **swd;
+ int klen;
+ uint32_t i;
+
+ stm32cryptoinfo("");
+
+ if (sid == NULL || cri == NULL)
+ {
+ return -EINVAL;
+ }
+
+ if (stm32_crypto_sessions)
+ {
+ for (i = 1; i < g_stm32_sesnum; i++)
+ {
+ if (stm32_crypto_sessions[i] == NULL)
+ {
+ break;
+ }
+ }
+ }
+
+ if (stm32_crypto_sessions == NULL || i == g_stm32_sesnum)
+ {
+ if (stm32_crypto_sessions == NULL)
+ {
+ i = 1; /* We leave stm32_crypto_sessions[0] empty */
+ g_stm32_sesnum = CRYPTO_SW_SESSIONS;
+ }
+ else
+ {
+ g_stm32_sesnum *= 2;
+ }
+
+ swd = kmm_calloc(g_stm32_sesnum, sizeof(struct stm32_crypto_data *));
+ if (swd == NULL)
+ {
+ /* Reset session number */
+
+ if (g_stm32_sesnum == CRYPTO_SW_SESSIONS)
+ {
+ g_stm32_sesnum = 0;
+ }
+ else
+ {
+ g_stm32_sesnum /= 2;
+ }
+
+ return -ENOBUFS;
+ }
+
+ /* Copy existing sessions */
+
+ if (stm32_crypto_sessions)
+ {
+ bcopy(stm32_crypto_sessions, swd,
+ (g_stm32_sesnum / 2) * sizeof(struct stm32_crypto_data *));
+ kmm_free(stm32_crypto_sessions);
+ }
+
+ stm32_crypto_sessions = swd;
+ }
+
+ swd = &stm32_crypto_sessions[i];
+ *sid = i;
+
+ while (cri)
+ {
+ *swd = kmm_zalloc(sizeof(struct stm32_crypto_data));
+ if (*swd == NULL)
+ {
+ stm32_freesession(i);
+ return -ENOBUFS;
+ }
+
+ switch (cri->cri_alg)
+ {
+ case CRYPTO_CRC32:
+ crc32_init(*swd);
+ break;
+ case CRYPTO_AES_CBC:
+ break;
+ case CRYPTO_AES_CTR:
+ klen = cri->cri_klen / 8 - 4;
+ if ((klen != 16) && (klen != 24) && (klen != 32))
+ {
+ /* stm32h7 aes-ctr key bits support 128, 192, or 256 */
+
+ return -EINVAL;
+ }
+
+ break;
+
+ default:
+ stm32_freesession(i);
+ return -EINVAL;
+ }
+
+ (*swd)->hw_alg = cri->cri_alg;
+ cri = cri->cri_next;
+ swd = &((*swd)->hw_next);
+ }
+
return 0;
}
@@ -106,13 +556,70 @@ static int stm32_freesession(uint64_t tid)
static int stm32_process(struct cryptop *crp)
{
+ FAR struct stm32_crypto_data *sw;
struct cryptodesc *crd;
uint8_t iv[AESCTR_BLOCKSIZE];
+ uint32_t lid;
+
+ stm32cryptoinfo("");
+
+ /* Sanity check */
+
+ if (crp == NULL)
+ {
+ return -EINVAL;
+ }
+
+ if (crp->crp_desc == NULL || crp->crp_buf == NULL)
+ {
+ crp->crp_etype = -EINVAL;
+ goto done;
+ }
+
+ lid = crp->crp_sid & 0xffffffff;
+ if (lid >= g_stm32_sesnum || lid == 0
+ || stm32_crypto_sessions[lid] == NULL)
+ {
+ crp->crp_etype = -ENOENT;
+ goto done;
+ }
+
+ /* Go through crypto descriptors, processing as we go */
for (crd = crp->crp_desc; crd; crd = crd->crd_next)
{
+ /* Find the crypto context.
+ * XXX Note that the logic here prevents us from having
+ * XXX the same algorithm multiple times in a session
+ * XXX (or rather, we can but it won't give us the right
+ * XXX results). To do that, we'd need some way of differentiating
+ * XXX between the various instances of an algorithm (so we can
+ * XXX locate the correct crypto context).
+ */
+
+ for (sw = stm32_crypto_sessions[lid];
+ sw && sw->hw_alg != crd->crd_alg;
+ sw = sw->hw_next);
+
+ /* No such context ? */
+
+ if (sw == NULL)
+ {
+ return -EINVAL;
+ }
+
switch (crd->crd_alg)
{
+ case CRYPTO_CRC32:
+ if (crd->crd_flags & CRD_F_UPDATE)
+ {
+ return crc32_update(sw, crp->crp_buf, crd->crd_len);
+ }
+ else
+ {
+ return crc32_final(sw, crp->crp_mac);
+ }
+ break;
case CRYPTO_AES_CBC:
return aes_cypher(crp->crp_dst, crp->crp_buf, crd->crd_len,
crp->crp_iv, crd->crd_key, 16,
@@ -134,6 +641,7 @@ static int stm32_process(struct cryptop *crp)
}
}
+ done:
return OK;
}
@@ -155,6 +663,8 @@ void hwcr_init(void)
memset(algs, 0, sizeof(algs));
+ algs[CRYPTO_CRC32] = CRYPTO_ALG_FLAG_SUPPORTED;
+
algs[CRYPTO_AES_CBC] = CRYPTO_ALG_FLAG_SUPPORTED;
algs[CRYPTO_AES_CTR] = CRYPTO_ALG_FLAG_SUPPORTED;
diff --git a/boards/arm/stm32h7/nucleo-h753zi/configs/crypto/defconfig
b/boards/arm/stm32h7/nucleo-h753zi/configs/crypto/defconfig
index 9f75e257f09..8a3031bd43d 100644
--- a/boards/arm/stm32h7/nucleo-h753zi/configs/crypto/defconfig
+++ b/boards/arm/stm32h7/nucleo-h753zi/configs/crypto/defconfig
@@ -48,10 +48,12 @@ CONFIG_SCHED_WAITPID=y
CONFIG_START_DAY=6
CONFIG_START_MONTH=12
CONFIG_START_YEAR=2011
+CONFIG_STM32_CRC=y
CONFIG_STM32_CRYP=y
CONFIG_STM32_USART3=y
CONFIG_SYSTEM_NSH=y
CONFIG_TASK_NAME_SIZE=0
CONFIG_TESTING_CRYPTO=y
+CONFIG_TESTING_CRYPTO_CRC32=y
CONFIG_TESTING_CRYPTO_STACKSIZE=4096
CONFIG_USART3_SERIAL_CONSOLE=y
