(nuttx) branch master updated: drivers/spi/ice40: fix operator precedence in final clock cycle count

[xiaoxiang]

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xiaoxiang781216 pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git


The following commit(s) were added to refs/heads/master by this push:
     new 864c97f1d91 drivers/spi/ice40: fix operator precedence in final clock 
cycle count
864c97f1d91 is described below

commit 864c97f1d911fccea0a8b202aaa65206ba2cb7a7
Author: yi chen <94x...@gmail.com>
AuthorDate: Sun Jul 12 22:04:22 2026 +0800

    drivers/spi/ice40: fix operator precedence in final clock cycle count
    
    ice40_endwrite() computes how many dummy SPI bytes to clock out after
    the bitstream to finish FPGA configuration with:
    
        for (size_t i = 0; i < ICE40_SPI_FINAL_CLK_CYCLES + 7 / 8; i++)
    
    `/` binds tighter than `+` in C, so this parses as
    ICE40_SPI_FINAL_CLK_CYCLES + (7 / 8) = 160 + 0 = 160, i.e. the "+ 7 / 8"
    is a silent no-op. The macro name and the classic `(n + 7) / 8`
    ceiling-division idiom (used elsewhere in embedded code to convert a
    bit/cycle count into a byte count) make clear the intent was to send
    ceil(ICE40_SPI_FINAL_CLK_CYCLES / 8) = 20 bytes (160 SPI clock cycles,
    matching the macro name). Instead the unmodified code sends 160 bytes,
    i.e. 1280 clock cycles - 8x more than intended.
    
    Fix by parenthesizing the ceiling-division: (ICE40_SPI_FINAL_CLK_CYCLES
    + 7) / 8, which evaluates to 20, restoring the intended 160-clock-cycle
    finalization sequence.
    
    Fixes #19367
    
    Assisted-by: Claude Code:claude-sonnet-5
    Signed-off-by: yi chen <94x...@gmail.com>
---
 drivers/spi/ice40.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/ice40.c b/drivers/spi/ice40.c
index 8cbfeb5641e..74ad372adad 100644
--- a/drivers/spi/ice40.c
+++ b/drivers/spi/ice40.c
@@ -269,7 +269,7 @@ ice40_endwrite(FAR struct ice40_dev_s *dev)
 
   dev->ops->select(dev, false);
 
-  for (size_t i = 0; i < ICE40_SPI_FINAL_CLK_CYCLES + 7 / 8; i++)
+  for (size_t i = 0; i < (ICE40_SPI_FINAL_CLK_CYCLES + 7) / 8; i++)
     {
       SPI_SEND(dev->spi, 0xff);
     }