igrr commented on code in PR #19772:
URL: https://github.com/apache/nuttx/pull/19772#discussion_r3758642861
##########
arch/xtensa/src/esp32s3/esp32s3_user.c:
##########
@@ -73,6 +77,30 @@ uint32_t *xtensa_user(int exccause, uint32_t *regs)
}
#endif /* CONFIG_ESPRESSIF_SPIFLASH */
+#ifdef CONFIG_ESP32S3_PAGEFAULT
+ /* A cache-attribute permission violation raises a precise, restartable
+ * exception: Load/Store/InstrFetch Prohibited (EXCCAUSE 28/29/20), with
+ * EXCVADDR holding the exact faulting address. This is proven on silicon
+ * (see esp32s3_pagefault.c) and is the recoverable-fault primitive. Offer
+ * these to the dispatcher; if serviced, return the register frame so that
+ * the RFE in the exception vector re-executes the faulting instruction.
+ *
+ * Note: ESP32-S3 PMS (World Controller) memory-protection violations are
+ * NOT delivered as these precise causes; they raise the asynchronous
+ * DRAM0/IRAM0 PMS-monitor interrupt instead (handled elsewhere).
Review Comment:
Could you please clarify where is "elsewhere"?
Could you please also mention and what is the observed outcome (on ESP32-S3)
when a process tries to access:
1. An internal RAM region to which access hasn't been granted
2. A PSRAM page to which access hasn't been granted
##########
arch/xtensa/src/esp32s3/esp32s3_user.c:
##########
@@ -73,6 +77,30 @@ uint32_t *xtensa_user(int exccause, uint32_t *regs)
}
#endif /* CONFIG_ESPRESSIF_SPIFLASH */
+#ifdef CONFIG_ESP32S3_PAGEFAULT
+ /* A cache-attribute permission violation raises a precise, restartable
+ * exception: Load/Store/InstrFetch Prohibited (EXCCAUSE 28/29/20), with
+ * EXCVADDR holding the exact faulting address. This is proven on silicon
+ * (see esp32s3_pagefault.c) and is the recoverable-fault primitive. Offer
+ * these to the dispatcher; if serviced, return the register frame so that
+ * the RFE in the exception vector re-executes the faulting instruction.
+ *
+ * Note: ESP32-S3 PMS (World Controller) memory-protection violations are
+ * NOT delivered as these precise causes; they raise the asynchronous
+ * DRAM0/IRAM0 PMS-monitor interrupt instead (handled elsewhere).
Review Comment:
Could you please clarify where is "elsewhere"?
Could you please also mention, what is the observed outcome (on ESP32-S3)
when a process tries to access:
1. An internal RAM region to which access hasn't been granted
2. A PSRAM page to which access hasn't been granted
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