wangtao13 commented on issue #19017:
URL: https://github.com/apache/nuttx/issues/19017#issuecomment-5260175495
I am not sure if I fixed the issue, the interrupt and exception are working.
I changed the chip_head.S as follows,
```
.section .bev_excpt,"ax",@progbits
.set noreorder
#ifdef CONFIG_MIPS_MICROMIPS
.set micromips
#endif
.ent _bev_exception
_bev_exception:
/* commented out by wt. la k0, _exception_handler */
la k0, _int_handler
jr k0
nop
.end _bev_exception
```
and
```
.section .int_handler, "ax", @progbits
.set noreorder
#ifdef CONFIG_MIPS_MICROMIPS
.set micromips
#endif
.ent _int_handler
_int_handler:
EXCPT_PROLOGUE t0 /* Save registers on stack, enable
nested interrupts */
move a0, sp /* Pass register save structure as the
parameter 1 */
USE_INTSTACK t0, t1, t2, t3 /* Switch to the interrupt stack */
la t0, mips_chip_decodeirq /* wt: Call mips_chip_decodeirq(regs)
*/
jalr ra, t0
nop
#ifdef CONFIG_MIPS_NESTED_INTERRUPTS
di /* Prohibit nested interrupts from here
*/
#endif
RESTORE_STACK t0, t1 /* Undo the operations of USE_STACK */
EXCPT_EPILOGUE v0 /* Return to the context returned by
mips_chip_decodeirq() */
.end _int_handler
```
Here is what I did in my porting of `up_irqinitialize()`.
```
/* Set all interrupts to the default (middle) priority */
/* Set the BEV bit in the STATUS register */
regval = cp0_getstatus();
regval |= CP0_STATUS_BEV;
cp0_putstatus(regval);
cp0_putebase(0x80000000);
/* Set the INTCTL vector spacing to non-zero */
cp0_putintctl(0x00000020);
/* Set the IV bit in the CAUSE register */
regval = cp0_getcause();
/// wt: Cleared IV
regval &= ~CP0_CAUSE_IV;
cp0_putcause(regval);
/* Clear the EXL and BEV bits in the STATUS register */
regval = cp0_getstatus();
regval &= ~(CP0_STATUS_EXL | CP0_STATUS_BEV);
cp0_putstatus(regval);
__asm__ volatile(
"sync\n\t"
"nop\n\t"
"nop\n\t"
"nop\n\t"
);
up_flush_dcache_all();
```
I found there supported a new MIPS SOC in arch/mips/src, I will check if I
can refer to its interrupt/exception configuration.
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