This is an automated email from the ASF dual-hosted git repository. GUIDINGLI pushed a commit to branch master in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit ab59b095a7192111d2fb345120e50660baf76759 Author: zhangyu117 <[email protected]> AuthorDate: Mon Aug 31 14:03:12 2026 +0800 arch/tricore: Simplify header files and implementation in FPU 1. replace __mtcr/mfcr with arch's tricore_mtcr/tricore_mfcr, donot dependon illd 2. Simplify header files 3. define registers address self Signed-off-by: zhangyu117 <[email protected]> --- arch/tricore/include/irq.h | 12 ++++++------ arch/tricore/src/common/tricore_fpu.c | 6 +++--- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/tricore/include/irq.h b/arch/tricore/include/irq.h index f4109c6f5bd..f2ff77438c5 100644 --- a/arch/tricore/include/irq.h +++ b/arch/tricore/include/irq.h @@ -147,14 +147,14 @@ /* FPU registers */ #ifdef CONFIG_ARCH_TC1V6 -# define FPU_SYNC_TRAP_REG CPU_FPU_TRAP_CON -# define FPU_ASYNC_TRAP_REG CPU_FPU_TRAP_CON +# define FPU_SYNC_TRAP_REG 0xA000 +# define FPU_ASYNC_TRAP_REG 0xA000 #else -# define FPU_SYNC_TRAP_REG CPU_FPU_SYNC_TRAP_CON -# define FPU_ASYNC_TRAP_REG CPU_FPU_TRAP_CON +# define FPU_SYNC_TRAP_REG 0xA030 +# define FPU_ASYNC_TRAP_REG 0xA000 #endif -#define FPU_TRAP_FZE_SHIFT 20 -#define FPU_TRAP_TCL_SHIFT 1 +#define FPU_TRAP_FZE_SHIFT 20 +#define FPU_TRAP_TCL_SHIFT 1 #ifndef __ASSEMBLY__ diff --git a/arch/tricore/src/common/tricore_fpu.c b/arch/tricore/src/common/tricore_fpu.c index ec1c4343e90..5b7c117d9c1 100644 --- a/arch/tricore/src/common/tricore_fpu.c +++ b/arch/tricore/src/common/tricore_fpu.c @@ -28,7 +28,7 @@ #include <string.h> -#include "tricore_internal.h" +#include <arch/irq.h> /**************************************************************************** * Public Functions @@ -42,8 +42,8 @@ void tricore_fpuinit(void) { /* FPU zero-divide trap enable */ - __mtcr(FPU_SYNC_TRAP_REG, - __mfcr(FPU_SYNC_TRAP_REG) | (1U << FPU_TRAP_FZE_SHIFT)); + tricore_mtcr(FPU_SYNC_TRAP_REG, tricore_mfcr(FPU_SYNC_TRAP_REG) | + (1U << FPU_TRAP_FZE_SHIFT)); } /****************************************************************************
