zhangyu-duck opened a new pull request, #20043: URL: https://github.com/apache/nuttx/pull/20043
### Summary Refactor NuttX's atomic operations to support inline arch-specific implementations, add new atomic types/variants, and provide 64-bit atomic support via spinlock. ### Commits 1. `include/atomic: add atomic_ptr_t type and operations` — add pointer-width atomic type and operations 2. `libc/atomic: support inline arch atomic for tricore` — tricore inline `atomic_*_4` via `swap.w`/`cmpswap.w` 3. `libc/atomic: support inline arch atomic for generic IRQ path` — generic IRQ/hwspinlock-based atomic path for archs without hardware atomics 4. `libc/atomic: merge tricore arch_atomic.c into machine/arch_atomic.c` — unify tricore atomic implementation into the generic `machine/arch_atomic.c` 5. `include/atomic: add cmpxchg_release_acquire memory order variant` — new cmpxchg memory order matching DPDK RTS ring tail-commit ordering 6. `libc: realize atomic64 via a spinlock helper` — 8-byte atomic symbols on a single spinlock for archs without native 64-bit support ### Impact - **New `atomic_ptr_t` type**: pointer-width atomic type and operations (commit 1) - **TriCore inline atomic**: `atomic_*_4` inlined via `swap.w`/`cmpswap.w` hardware instructions, no function call overhead (commit 2) - **Generic IRQ/hwspinlock path**: archs without hardware atomics get inline atomic via IRQ disable or hwspinlock (commit 3) - **Unification**: tricore-specific `arch_atomic.c` merged into generic `machine/arch_atomic.c` (commit 4) - **New memory order**: `atomic_cmpxchg_release_acquire` and `atomic_try_cmpxchg_release_acquire` for 32/64/pointer-width (commit 5) - **64-bit atomics**: all `atomic_*_8`, `__atomic_*_8`, `sync_*_8`, `__sync_*_8` symbols provided via `libs/libc/machine/arch_atomic64.c` on a single spinlock (`g_atomic64_lock`), using `spin_lock_irqsave` for SMP correctness and local ISR safety; all helpers `weak_function` so archs with native 64-bit support can override at link time (commit 6) ### Testing - [ ] Compile-test on TriCore (lzcu / tc4d9_evb_bmp) - [ ] Runtime test on hardware - [ ] SMP correctness verification for the 64-bit atomic spinlock path ### Notes - Commits 1-5 ported from `vela/dev-system` (original author: Bowen Wang <[email protected]>; DCO preserved via `Signed-off-by`) - Commit 6 (`atomic64` spinlock helper) is original work by zhangyu117 <[email protected]> 🤖 Generated with [Claude Code](https://claude.com/claude-code) -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
