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xiaoxiang781216 pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
The following commit(s) were added to refs/heads/master by this push:
new 9b9d87b69c7 arch/atomic: remove up_testset in spinlock
9b9d87b69c7 is described below
commit 9b9d87b69c7eed5cb67404d7654c6637020f711b
Author: zhangyu117 <[email protected]>
AuthorDate: Thu Aug 21 13:35:50 2025 +0800
arch/atomic: remove up_testset in spinlock
Remove the per-arch testset implementation from the spinlock layer.
The testset abstraction predates the unified spinlock.h API and is no
longer used now that all arches provide spin_lock_irqsave()/
spin_unlock_irqrestore() directly. Drop the per-arch *_testset.{c,S}
implementations and spinlock.h files for arm, sim, sparc, tricore,
x86_64, and xtensa, along with the CXD56_TESTSET,
CXD56_TESTSET_WITH_HWSEM, and CXD56_ATOMIC_WITH_HWSEM Kconfig options
in arch/arm/src/cxd56xx, and simplify the CXD56 semaphore pool loop
in cxd56_sph.c to a single unconditional range.
Signed-off-by: zhangyu117 <[email protected]>
---
Documentation/implementation/smp.rst | 18 +-
Documentation/reference/os/smp.rst | 13 --
Documentation/reference/user/13_boardctl.rst | 15 --
arch/Kconfig | 15 --
arch/arm/Kconfig | 60 ------
arch/arm/include/arch.h | 7 +
arch/arm/include/spinlock.h | 129 -------------
arch/arm/src/common/CMakeLists.txt | 4 -
arch/arm/src/common/Make.defs | 3 -
arch/arm/src/common/gnu/arm_fetchadd.S | 269 ---------------------------
arch/arm/src/common/iar/arm_fetchadd.S | 225 ----------------------
arch/arm/src/cxd56xx/CMakeLists.txt | 3 -
arch/arm/src/cxd56xx/Kconfig | 15 --
arch/arm/src/cxd56xx/Make.defs | 4 -
arch/arm/src/cxd56xx/cxd56_atomic.c | 2 +-
arch/arm/src/cxd56xx/cxd56_sph.c | 6 +-
arch/arm/src/cxd56xx/cxd56_testset.c | 125 -------------
arch/arm/src/lc823450/Make.defs | 2 -
arch/arm/src/lc823450/lc823450_testset.c | 101 ----------
arch/arm/src/rp2040/CMakeLists.txt | 3 +-
arch/arm/src/rp2040/Make.defs | 2 -
arch/arm/src/rp2040/rp2040_testset.c | 86 ---------
arch/arm/src/rp23xx/CMakeLists.txt | 3 +-
arch/arm/src/rp23xx/Make.defs | 2 -
arch/arm/src/rp23xx/rp23xx_testset.c | 92 ---------
arch/arm/src/s32k1xx/Kconfig | 1 -
arch/arm/src/s32k3xx/Kconfig | 1 -
arch/arm64/Kconfig | 8 +-
arch/arm64/include/arch.h | 4 +
arch/arm64/include/spinlock.h | 115 ------------
arch/ceva/include/arch.h | 1 +
arch/ceva/include/spinlock.h | 105 -----------
arch/ceva/include/xc5/spinlock.h | 30 ---
arch/ceva/include/xm6/spinlock.h | 127 -------------
arch/risc-v/Kconfig | 2 -
arch/risc-v/include/arch.h | 2 +
arch/risc-v/include/spinlock.h | 135 --------------
arch/sim/include/spinlock.h | 75 --------
arch/sim/src/Makefile | 4 -
arch/sim/src/sim/CMakeLists.txt | 4 -
arch/sim/src/sim/posix/sim_testset.c | 74 --------
arch/sparc/Kconfig | 1 -
arch/sparc/include/spinlock.h | 84 ---------
arch/sparc/src/common/Make.defs | 4 -
arch/sparc/src/common/sparc_testset.c | 106 -----------
arch/tricore/Kconfig | 2 -
arch/tricore/include/arch.h | 2 +
arch/tricore/include/spinlock.h | 89 ---------
arch/tricore/src/common/CMakeLists.txt | 4 -
arch/tricore/src/common/Make.defs | 4 -
arch/tricore/src/common/tricore_testset.c | 63 -------
arch/x86_64/include/arch.h | 4 +-
arch/x86_64/include/spinlock.h | 99 ----------
arch/x86_64/src/intel64/CMakeLists.txt | 4 -
arch/x86_64/src/intel64/Make.defs | 4 -
arch/x86_64/src/intel64/intel64_testset.S | 73 --------
arch/xtensa/Kconfig | 2 -
arch/xtensa/include/spinlock.h | 106 -----------
include/nuttx/arch.h | 72 -------
include/nuttx/spinlock.h | 115 ++----------
include/nuttx/spinlock_type.h | 13 +-
sched/Kconfig | 1 -
62 files changed, 53 insertions(+), 2691 deletions(-)
diff --git a/Documentation/implementation/smp.rst
b/Documentation/implementation/smp.rst
index 2663db51e2c..5b2548849a7 100644
--- a/Documentation/implementation/smp.rst
+++ b/Documentation/implementation/smp.rst
@@ -50,7 +50,7 @@ SMP can be enabled on NuttX with the following configuration
settings:
This setting provides the stack size for the IDLE task on CPUS 1
through ``(CONFIG_SMP_NCPUS-1)``.
-This section provides the origin design specification for the implemention.
+This section provides the origin design specification for the implementation.
As a result, you may find that the test uses future and conditional tenses
when describing the implementation of SMP on NuttX.
@@ -189,7 +189,7 @@ The Current Task
----------------
There is a lot of logic in the RTOS now that obtains the TCB for the currently
-excuting task by examining the head of the ``g_readytorun`` list.
+executing task by examining the head of the ``g_readytorun`` list.
You will see this assignment in many places, both in the core OS logic
in ``nuttx/sched`` but also in architecture-specific logic under
``nuttx/arch``:
@@ -495,11 +495,9 @@ The following new, internal OS interfaces are proposed:
void spin_unlock(FAR spinlock_t *lock);
Where the type ``spinlock_t`` is defined in MCU-specific header files.
-These new spinlock interfaces would also use the MCU-specific interface:
-
-.. code-block:: c
-
- spinlock_t up_testset(FAR spinlock_t *lock);
+These spinlock interfaces are implemented using the generic atomic
+operations provided by :file:`include/nuttx/atomic.h`
+(e.g. :c:func:`atomic_xchg_acquire`, :c:func:`atomic_cmpxchg_acquire`).
.. note::
@@ -509,7 +507,7 @@ These new spinlock interfaces would also use the
MCU-specific interface:
Yes, probably. One solution might be lock the thread
to a CPU if it holds the lock?
-There is also a risk is that the thread holding the lock will be pre-empted
+There is also a risk is that the thread holding the lock will be preempted
by the OS scheduler while holding the lock. If this happens, other threads
on other CPUs will be left spinning (repeatedly trying to acquire the lock),
while the thread holding the lock is not making progress towards releasing it.
@@ -586,7 +584,7 @@ CPU resources.
Thus, ``sched_lock()`` and its companion, ``sched_unlcok()``,
are used to implement some critical sections.
-Currnetly, Pre-emption is disabled using a simple lockcount in the TCB.
+Currently, Pre-emption is disabled using a simple lockcount in the TCB.
When the scheduling is locked, the lockcount is incremented;
when the scheduler is unlocked, the lockcount is decremented.
If the lockcount for the task at the head of the ``g_readytorun``
@@ -833,7 +831,7 @@ in ``sched.h``.
int sched_getaffinity(pid_t pid, size_t cpusetsize, FAR cpu_set_t *mask);
#endif
-There are similar interfaces for a ``pthread`` prototyped in ``phtread.h``:
+There are similar interfaces for a ``pthread`` prototyped in ``pthread.h``:
.. code-block:: c
diff --git a/Documentation/reference/os/smp.rst
b/Documentation/reference/os/smp.rst
index a4ae7913668..bcc07161f0a 100644
--- a/Documentation/reference/os/smp.rst
+++ b/Documentation/reference/os/smp.rst
@@ -24,19 +24,6 @@ For a technical description of the NuttX implementation of
SMP,
see the NuttX `SMP Wiki
Page <https://cwiki.apache.org/confluence/display/NUTTX/SMP>`__.
-.. c:function:: spinlock_t up_testset(volatile FAR spinlock_t *lock)
-
- Perform and atomic test and set operation on the provided spinlock.
-
- :param lock: The address of spinlock object.
-
- :return: The spinlock is always locked upon return. The value
- of previous value of the spinlock variable is returned,
- either SP_LOCKED if the spinlock was previously locked
- (meaning that the test-and-set operation failed to obtain the lock)
- or SP_UNLOCKED if the spinlock was previously unlocked
- (meaning that we successfully obtained the lock)
-
.. c:function:: int up_cpu_index(void)
Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1)
diff --git a/Documentation/reference/user/13_boardctl.rst
b/Documentation/reference/user/13_boardctl.rst
index 6cd765862d8..a182ddf69e2 100644
--- a/Documentation/reference/user/13_boardctl.rst
+++ b/Documentation/reference/user/13_boardctl.rst
@@ -228,18 +228,3 @@ Graphics
:dependencies: Base NX terminal logic provides :c:func:`nxterm_ioctl_tap`.
-Testing
--------
-
-.. c:macro:: BOARDIOC_TESTSET
-
- Access architecture-specific up_testset() operation
-
- :Argument: A pointer to a write-able spinlock object. On success
- the preceding spinlock state is returned: 0=unlocked,
- 1=locked.
-
- :configuration: CONFIG_BOARDCTL_TESTSET
-
- :dependencies: Architecture-specific logic provides :c:func:`up_testset`.
-
diff --git a/arch/Kconfig b/arch/Kconfig
index 6fb20d745ee..3de2bd2caf4 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -110,7 +110,6 @@ config ARCH_SIM
select ARCH_HAVE_SYSCALL_HOOKS
select ARCH_HAVE_TICKLESS
select ARCH_HAVE_POWEROFF
- select ARCH_HAVE_TESTSET
select ARCH_HAVE_VFORK if !HOST_WINDOWS
select ARCH_HAVE_SETJMP
select ARCH_HAVE_CUSTOMOPT
@@ -141,7 +140,6 @@ config ARCH_X86_64
select ARCH_HAVE_FPU
select ARCH_HAVE_DPFPU
select ARCH_HAVE_MULTICPU
- select ARCH_HAVE_TESTSET
select ARCH_HAVE_INTERRUPTSTACK
select ARCH_HAVE_CUSTOMOPT
select ARCH_HAVE_THREAD_LOCAL
@@ -624,23 +622,10 @@ config ARCH_HAVE_DYNAMIC_UDELAY
after a failure - the implementation should always re-read
current
hardware settings as anything stored in memory may be
corrupted.)
-config ARCH_HAVE_TESTSET
- bool
- default n
-
-config ARCH_HAVE_CUSTOM_TESTSET
- bool
- default n
- select ARCH_HAVE_TESTSET
-
config ARCH_HAVE_THREAD_LOCAL
bool
default n
-config ARCH_HAVE_FETCHADD
- bool
- default n
-
config ARCH_HAVE_RTC_SUBSECONDS
bool
default n
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5721c73b3c7..6a96c672816 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -63,7 +63,6 @@ config ARCH_CHIP_A1X
select ARM_HAVE_NEON
select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_LOWVECTORS
- select ARCH_HAVE_FETCHADD
select ARCH_HAVE_SDRAM
depends on BOOT_RUNFROMSDRAM
select ARCH_HAVE_ADDRENV
@@ -77,7 +76,6 @@ config ARCH_CHIP_AM335X
select ARM_HAVE_NEON
select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_LOWVECTORS
- select ARCH_HAVE_FETCHADD
select ARCH_HAVE_SDRAM
depends on BOOT_RUNFROMSDRAM
select ARCH_HAVE_ADDRENV
@@ -88,7 +86,6 @@ config ARCH_CHIP_AM335X
config ARCH_CHIP_AM67
bool "AM67"
select ARCH_CORTEXR5
- select ARCH_HAVE_FETCHADD
select ARCH_HAVE_LOWVECTORS
select ARCH_HAVE_TICKLESS
---help---
@@ -98,7 +95,6 @@ config ARCH_CHIP_FVP_ARMV8R_AARCH32
bool "ARM FVP virt platform (ARMv8r AARCH32)"
select ARCH_CORTEXR52
select ARCH_HAVE_LOWVECTORS
- select ARCH_HAVE_FETCHADD
select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_HIPRI_INTERRUPT
select ARCH_HAVE_FPU
@@ -116,7 +112,6 @@ config ARCH_CHIP_C5471
config ARCH_CHIP_CSK6
bool "LISTEANAI CSK6 6001A/6011B/6012"
select ARCH_HAVE_MPU
- select ARCH_HAVE_FETCHADD
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_HEAPCHECK
select ARCH_HAVE_PROGMEM
@@ -139,7 +134,6 @@ config ARCH_CHIP_DM320
config ARCH_CHIP_EFM32
bool "Energy Micro EFM32"
select ARCH_HAVE_SPI_BITORDER
- select ARCH_HAVE_FETCHADD
---help---
Energy Micro EFM32 microcontrollers (ARM Cortex-M).
@@ -156,7 +150,6 @@ config ARCH_CHIP_GD32F4
bool "GD32MCU GD32 F4"
select ARCH_CORTEXM4
select ARCH_HAVE_MPU
- select ARCH_HAVE_FETCHADD
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_HEAPCHECK
select ARCH_HAVE_PROGMEM
@@ -183,7 +176,6 @@ config ARCH_CHIP_IMX6
select ARM_HAVE_NEON
select ARCH_HAVE_TRUSTZONE
select ARCH_HAVE_LOWVECTORS
- select ARCH_HAVE_FETCHADD
select ARCH_HAVE_SDRAM
depends on BOOT_RUNFROMSDRAM
select ARCH_HAVE_ADDRENV
@@ -195,7 +187,6 @@ config ARCH_CHIP_IMX9_CORTEX_M
bool "NXP iMX.9 Cortex-M7"
select ARCH_CORTEXM7
select ARCH_HAVE_MPU
- select ARCH_HAVE_FETCHADD
select ARCH_HAVE_RAMFUNCS
select ARCH_HAVE_TICKLESS
select ARCH_HAVE_I2CRESET
@@ -209,7 +200,6 @@ config ARCH_CHIP_IMXRT
bool "NXP/Freescale iMX.RT"
select ARCH_CORTEXM7
select ARCH_HAVE_MPU
- select ARCH_HAVE_FETCHADD
select ARCH_HAVE_RAMFUNCS
select ARCH_HAVE_TICKLESS
select ARCH_HAVE_I2CRESET
@@ -225,7 +215,6 @@ config ARCH_CHIP_KINETIS
select ARCH_HAVE_MPU
select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_FPU
- select ARCH_HAVE_FETCHADD
select ARCH_HAVE_RAMFUNCS
select ARCH_HAVE_I2CRESET
---help---
@@ -244,7 +233,6 @@ config ARCH_CHIP_LC823450
select ARCH_HAVE_HEAPCHECK
select ARCH_HAVE_MULTICPU
select ARCH_HAVE_I2CRESET
- select ARCH_HAVE_CUSTOM_TESTSET
---help---
ON Semiconductor LC823450 architectures (ARM dual Cortex-M3)
@@ -259,7 +247,6 @@ config ARCH_CHIP_LPC17XX_40XX
bool "NXP LPC17xx/LPC40xx"
select ARCH_HAVE_MPU
select ARM_HAVE_MPU_UNIFIED
- select ARCH_HAVE_FETCHADD
select ARMV7M_HAVE_STACKCHECK
---help---
NXP LPC17xx & LPC40xx architectures (ARM Cortex-M3/4)
@@ -291,7 +278,6 @@ config ARCH_CHIP_LPC43XX
select ARCH_HAVE_MPU
select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_FPU
- select ARCH_HAVE_FETCHADD
---help---
NPX LPC43XX architectures (ARM Cortex-M4).
@@ -301,13 +287,11 @@ config ARCH_CHIP_LPC54XX
select ARCH_HAVE_MPU
select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_FPU
- select ARCH_HAVE_FETCHADD
---help---
NPX LPC54XX architectures (ARM Cortex-M4).
config ARCH_CHIP_MAX326XX
bool "Maxim Integrated MAX326XX"
- select ARCH_HAVE_FETCHADD
---help---
Maxim Integrated MAX326XX microcontrollers (ARM Cortex-M4F).
@@ -380,7 +364,6 @@ config ARCH_CHIP_RP2040
select ARCH_HAVE_I2CRESET
select ARM_HAVE_WFE_SEV
select ARCH_BOARD_COMMON
- select ARCH_HAVE_CUSTOM_TESTSET
select ARCH_USBDEV_STALLQUEUE if USBDEV
select LIBC_ATOMIC_IRQ if !SMP
select LIBC_ATOMIC_HWSPINLOCK if SMP
@@ -396,7 +379,6 @@ config ARCH_CHIP_RP23XX
select ARM_HAVE_WFE_SEV
select ARM_HAVE_DSP
select ARCH_HAVE_FPU
- select ARCH_HAVE_CUSTOM_TESTSET
select ARCH_HAVE_TICKLESS
select ARCH_BOARD_COMMON
select ARCH_USBDEV_STALLQUEUE if USBDEV
@@ -426,7 +408,6 @@ config ARCH_CHIP_SAMA5
select ARCH_CORTEXA5
select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_LOWVECTORS
- select ARCH_HAVE_FETCHADD
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_TICKLESS
select ARCH_HAVE_ADDRENV
@@ -463,7 +444,6 @@ config ARCH_CHIP_SAM34
bool "Atmel SAM3/SAM4"
select ARCH_HAVE_MPU
select ARM_HAVE_MPU_UNIFIED
- select ARCH_HAVE_FETCHADD
select ARCH_HAVE_RAMFUNCS
select ARMV7M_HAVE_STACKCHECK
---help---
@@ -473,7 +453,6 @@ config ARCH_CHIP_SAMV7
bool "Atmel SAMV7"
select ARCH_CORTEXM7
select ARCH_HAVE_MPU
- select ARCH_HAVE_FETCHADD
select ARCH_HAVE_PROGMEM
select ARCH_HAVE_RAMFUNCS
select ARCH_HAVE_TICKLESS
@@ -489,7 +468,6 @@ config ARCH_CHIP_SIMPLELINK
bool "TI SimpleLink"
select ARCH_HAVE_MPU
select ARM_HAVE_MPU_UNIFIED
- select ARCH_HAVE_FETCHADD
depends on EXPERIMENTAL
---help---
TI SimpleLink CCxxx architectures (ARM Cortex-M3 or M4)
@@ -498,7 +476,6 @@ config ARCH_CHIP_STM32F1
bool "STMicro STM32 F1"
select ARCH_CHIP_STM32
select ARCH_HAVE_MPU
- select ARCH_HAVE_FETCHADD
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_HEAPCHECK
select ARCH_HAVE_PROGMEM
@@ -515,7 +492,6 @@ config ARCH_CHIP_STM32F2
bool "STMicro STM32 F2"
select ARCH_CHIP_STM32
select ARCH_HAVE_MPU
- select ARCH_HAVE_FETCHADD
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_HEAPCHECK
select ARCH_HAVE_PROGMEM
@@ -532,7 +508,6 @@ config ARCH_CHIP_STM32F3
bool "STMicro STM32 F3"
select ARCH_CHIP_STM32
select ARCH_HAVE_MPU
- select ARCH_HAVE_FETCHADD
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_HEAPCHECK
select ARCH_HAVE_PROGMEM
@@ -549,7 +524,6 @@ config ARCH_CHIP_STM32F4
bool "STMicro STM32 F4"
select ARCH_CHIP_STM32
select ARCH_HAVE_MPU
- select ARCH_HAVE_FETCHADD
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_HEAPCHECK
select ARCH_HAVE_PROGMEM
@@ -566,7 +540,6 @@ config ARCH_CHIP_STM32G4
bool "STMicro STM32 G4"
select ARCH_CHIP_STM32
select ARCH_HAVE_MPU
- select ARCH_HAVE_FETCHADD
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_HEAPCHECK
select ARCH_HAVE_PROGMEM
@@ -583,7 +556,6 @@ config ARCH_CHIP_STM32L1
bool "STMicro STM32 L1"
select ARCH_CHIP_STM32
select ARCH_HAVE_MPU
- select ARCH_HAVE_FETCHADD
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_HEAPCHECK
select ARCH_HAVE_PROGMEM
@@ -637,7 +609,6 @@ config ARCH_CHIP_STM32F7
select ARCH_CHIP_STM32
select ARCH_CORTEXM7
select ARCH_HAVE_MPU
- select ARCH_HAVE_FETCHADD
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_HEAPCHECK
select ARCH_HAVE_PROGMEM
@@ -670,7 +641,6 @@ config ARCH_CHIP_STM32L4
select ARCH_CHIP_STM32
select ARCH_CORTEXM4
select ARCH_HAVE_MPU
- select ARCH_HAVE_FETCHADD
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_HEAPCHECK
select ARCH_HAVE_PROGMEM
@@ -687,7 +657,6 @@ config ARCH_CHIP_STM32H5
select ARCH_CORTEXM33
select ARCH_HAVE_MPU
select ARM_HAVE_DSP
- select ARCH_HAVE_FETCHADD
select ARCH_HAVE_HEAPCHECK
select ARCH_HAVE_PROGMEM
select ARCH_HAVE_SPI_BITORDER
@@ -706,7 +675,6 @@ config ARCH_CHIP_STM32N6
select ARM_HAVE_DSP
select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_TRUSTZONE
- select ARCH_HAVE_FETCHADD
select ARCH_HAVE_HEAPCHECK
---help---
STMicro STM32N6 architectures (ARM Cortex-M55).
@@ -717,7 +685,6 @@ config ARCH_CHIP_STM32L5
select ARCH_CORTEXM33
select ARCH_HAVE_MPU
select ARM_HAVE_DSP
- select ARCH_HAVE_FETCHADD
select ARCH_HAVE_HEAPCHECK
select ARCH_HAVE_PROGMEM
select ARCH_HAVE_SPI_BITORDER
@@ -733,7 +700,6 @@ config ARCH_CHIP_STM32U5
select ARCH_CORTEXM33
select ARCH_HAVE_MPU
select ARM_HAVE_DSP
- select ARCH_HAVE_FETCHADD
select ARCH_HAVE_HEAPCHECK
select ARCH_HAVE_HEAP2
select ARCH_HAVE_PROGMEM
@@ -750,7 +716,6 @@ config ARCH_CHIP_STM32U3
select ARCH_CORTEXM33
select ARCH_HAVE_MPU
select ARM_HAVE_DSP
- select ARCH_HAVE_FETCHADD
select ARCH_HAVE_HEAPCHECK
select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_TRUSTZONE
@@ -763,7 +728,6 @@ config ARCH_CHIP_STM32C5
select ARCH_CORTEXM33
select ARCH_HAVE_MPU
select ARM_HAVE_DSP
- select ARCH_HAVE_FETCHADD
select ARCH_HAVE_HEAPCHECK
select ARM_HAVE_MPU_UNIFIED
---help---
@@ -775,7 +739,6 @@ config ARCH_CHIP_STM32WB
select ARCH_CORTEXM4
select ARCH_HAVE_FPU
select ARCH_HAVE_MPU
- select ARCH_HAVE_FETCHADD
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_HEAPCHECK
select ARCH_HAVE_PROGMEM
@@ -791,7 +754,6 @@ config ARCH_CHIP_STM32WL5
select ARCH_CHIP_STM32
select ARCH_CORTEXM4
select ARCH_HAVE_MPU
- select ARCH_HAVE_FETCHADD
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_HEAPCHECK
select ARCH_HAVE_PROGMEM
@@ -813,7 +775,6 @@ config ARCH_CHIP_TMS570
bool "TI TMS570"
select ENDIAN_BIG
select ARCH_HAVE_LOWVECTORS
- select ARCH_HAVE_FETCHADD
select ARCH_HAVE_RAMFUNCS
select ARMV7R_MEMINIT
select ARMV7R_HAVE_DECODEFIQ
@@ -824,7 +785,6 @@ config ARCH_CHIP_TIVA
bool "TI Tiva"
select ARCH_HAVE_MPU
select ARM_HAVE_MPU_UNIFIED
- select ARCH_HAVE_FETCHADD
---help---
TI Tiva TM4C architectures (ARM Cortex-M4)
@@ -832,7 +792,6 @@ config ARCH_CHIP_XMC4
bool "Infineon XMC4xxx"
select ARCH_CORTEXM4
select ARCH_HAVE_MPU
- select ARCH_HAVE_FETCHADD
select ARCH_HAVE_RAMFUNCS
select ARCH_HAVE_I2CRESET
select ARM_HAVE_MPU_UNIFIED
@@ -845,7 +804,6 @@ config ARCH_CHIP_MX8MP
bool "NXP i.MX8MP"
select ARCH_CORTEXM7
select ARCH_HAVE_MPU
- select ARCH_HAVE_FETCHADD
select ARCH_HAVE_RAMFUNCS
select ARCH_HAVE_I2CRESET
select ARM_HAVE_MPU_UNIFIED
@@ -869,7 +827,6 @@ config ARCH_CHIP_CXD56XX
select ARCH_HAVE_SDIO if MMCSD
select ARCH_HAVE_MATH_H
select ARCH_HAVE_I2CRESET
- select ARCH_HAVE_CUSTOM_TESTSET
---help---
Sony CXD56XX (ARM Cortex-M4) architectures
@@ -945,7 +902,6 @@ config ARCH_CHIP_GOLDFISH_ARM
config ARCH_CHIP_AT32
bool "Artery AT32 F4"
select ARCH_HAVE_MPU
- select ARCH_HAVE_FETCHADD
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_HEAPCHECK
select ARCH_HAVE_PROGMEM
@@ -1108,7 +1064,6 @@ config ARCH_CORTEXM3
select ARCH_HAVE_RAMVECTORS
select ARCH_HAVE_HIPRI_INTERRUPT
select ARCH_HAVE_RESET
- select ARCH_HAVE_TESTSET
select ARCH_HAVE_HARDFAULT_DEBUG
select ARCH_HAVE_MEMFAULT_DEBUG
select ARCH_HAVE_BUSFAULT_DEBUG
@@ -1124,7 +1079,6 @@ config ARCH_CORTEXM4
select ARCH_HAVE_RAMVECTORS
select ARCH_HAVE_HIPRI_INTERRUPT
select ARCH_HAVE_RESET
- select ARCH_HAVE_TESTSET
select ARCH_HAVE_HARDFAULT_DEBUG
select ARCH_HAVE_MEMFAULT_DEBUG
select ARCH_HAVE_BUSFAULT_DEBUG
@@ -1141,7 +1095,6 @@ config ARCH_CORTEXM7
select ARCH_HAVE_RAMVECTORS
select ARCH_HAVE_HIPRI_INTERRUPT
select ARCH_HAVE_RESET
- select ARCH_HAVE_TESTSET
select ARCH_HAVE_HARDFAULT_DEBUG
select ARCH_HAVE_MEMFAULT_DEBUG
select ARCH_HAVE_BUSFAULT_DEBUG
@@ -1163,7 +1116,6 @@ config ARCH_CORTEXA5
select ARCH_ICACHE
select ARCH_HAVE_MMU
select ARCH_USE_MMU
- select ARCH_HAVE_TESTSET
select ARM_HAVE_MPCORE
config ARCH_CORTEXA7
@@ -1174,7 +1126,6 @@ config ARCH_CORTEXA7
select ARCH_ICACHE
select ARCH_HAVE_MMU
select ARCH_USE_MMU
- select ARCH_HAVE_TESTSET
select ARCH_HAVE_FPU
select ARM_HAVE_MPCORE
@@ -1186,7 +1137,6 @@ config ARCH_CORTEXA8
select ARCH_ICACHE
select ARCH_HAVE_MMU
select ARCH_USE_MMU
- select ARCH_HAVE_TESTSET
config ARCH_CORTEXA9
bool
@@ -1196,7 +1146,6 @@ config ARCH_CORTEXA9
select ARCH_ICACHE
select ARCH_HAVE_MMU
select ARCH_USE_MMU
- select ARCH_HAVE_TESTSET
select ARM_HAVE_MPCORE
config ARCH_ARMV7R
@@ -1213,7 +1162,6 @@ config ARCH_CORTEXR4
select ARCH_DCACHE
select ARCH_ICACHE
select ARCH_HAVE_MPU
- select ARCH_HAVE_TESTSET
config ARCH_CORTEXR5
bool
@@ -1222,7 +1170,6 @@ config ARCH_CORTEXR5
select ARCH_DCACHE
select ARCH_ICACHE
select ARCH_HAVE_MPU
- select ARCH_HAVE_TESTSET
config ARCH_CORTEXR7
bool
@@ -1231,14 +1178,12 @@ config ARCH_CORTEXR7
select ARCH_DCACHE
select ARCH_ICACHE
select ARCH_HAVE_MPU
- select ARCH_HAVE_TESTSET
config ARCH_CORTEXR52
bool
default n
select ARCH_ARMV8R
select ARCH_HAVE_MPU
- select ARCH_HAVE_TESTSET
config ARCH_ARMV8M
bool
@@ -1257,7 +1202,6 @@ config ARCH_CORTEXM23
select ARCH_HAVE_RAMVECTORS
select ARCH_HAVE_HIPRI_INTERRUPT
select ARCH_HAVE_RESET
- select ARCH_HAVE_TESTSET
select ARCH_HAVE_HARDFAULT_DEBUG
config ARCH_CORTEXM33
@@ -1270,7 +1214,6 @@ config ARCH_CORTEXM33
select ARCH_HAVE_RAMVECTORS
select ARCH_HAVE_HIPRI_INTERRUPT
select ARCH_HAVE_RESET
- select ARCH_HAVE_TESTSET
select ARCH_HAVE_HARDFAULT_DEBUG
select ARCH_HAVE_MEMFAULT_DEBUG
select ARCH_HAVE_BUSFAULT_DEBUG
@@ -1287,7 +1230,6 @@ config ARCH_CORTEXM35P
select ARCH_HAVE_RAMVECTORS
select ARCH_HAVE_HIPRI_INTERRUPT
select ARCH_HAVE_RESET
- select ARCH_HAVE_TESTSET
select ARCH_HAVE_HARDFAULT_DEBUG
select ARCH_HAVE_MEMFAULT_DEBUG
select ARCH_HAVE_BUSFAULT_DEBUG
@@ -1304,7 +1246,6 @@ config ARCH_CORTEXM55
select ARCH_HAVE_RAMVECTORS
select ARCH_HAVE_HIPRI_INTERRUPT
select ARCH_HAVE_RESET
- select ARCH_HAVE_TESTSET
select ARCH_HAVE_HARDFAULT_DEBUG
select ARCH_HAVE_MEMFAULT_DEBUG
select ARCH_HAVE_BUSFAULT_DEBUG
@@ -1321,7 +1262,6 @@ config ARCH_CORTEXM85
select ARCH_HAVE_RAMVECTORS
select ARCH_HAVE_HIPRI_INTERRUPT
select ARCH_HAVE_RESET
- select ARCH_HAVE_TESTSET
select ARCH_HAVE_HARDFAULT_DEBUG
select ARCH_HAVE_MEMFAULT_DEBUG
select ARCH_HAVE_BUSFAULT_DEBUG
diff --git a/arch/arm/include/arch.h b/arch/arm/include/arch.h
index 786f7e6cbd2..a91136c4662 100644
--- a/arch/arm/include/arch.h
+++ b/arch/arm/include/arch.h
@@ -37,6 +37,8 @@
# include <nuttx/pgalloc.h>
#endif
+#include <arch/barriers.h>
+
/****************************************************************************
* Pre-processor Prototypes
****************************************************************************/
@@ -114,6 +116,11 @@ do { \
# define _einit Image$$init_section$$Limit
#endif
+#ifdef CONFIG_ARM_HAVE_WFE_SEV
+# define UP_WFE() __asm__ __volatile__ ("wfe" : : : "memory")
+# define UP_SEV() __asm__ __volatile__ ("sev" : : : "memory")
+#endif
+
/****************************************************************************
* Inline functions
****************************************************************************/
diff --git a/arch/arm/include/spinlock.h b/arch/arm/include/spinlock.h
deleted file mode 100644
index a2ca0006137..00000000000
--- a/arch/arm/include/spinlock.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/****************************************************************************
- * arch/arm/include/spinlock.h
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements. See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership. The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-#ifndef __ARCH_ARM_INCLUDE_SPINLOCK_H
-#define __ARCH_ARM_INCLUDE_SPINLOCK_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-# include <stdint.h>
-#endif /* __ASSEMBLY__ */
-
-#include <arch/barriers.h>
-
-/****************************************************************************
- * Pre-processor Prototypes
- ****************************************************************************/
-
-/* Spinlock states */
-
-#define SP_UNLOCKED 0 /* The Un-locked state */
-#define SP_LOCKED 1 /* The Locked state */
-
-#ifdef CONFIG_ARM_HAVE_WFE_SEV
-# ifndef UP_WFE
-# define UP_WFE() __asm__ __volatile__ ("wfe" : : : "memory")
-# endif
-# ifndef UP_SEV
-# define UP_SEV() __asm__ __volatile__ ("sev" : : : "memory")
-# endif
-#endif
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/* The Type of a spinlock.
- *
- * ARMv6 architecture introduced the concept of exclusive accesses to memory
- * locations in the form of the Load-Exclusive (LDREX) and Store-Exclusive
- * (STREX) instructions in ARM and Thumb instruction sets. ARMv6K extended
- * this to included byte, halfword, and doubleword variants of LDREX and
- * STREX. ARMv7-M supports byte and halfword, but not the doubleword variant
- * (ARMv6-M does not support exclusive access).
- *
- * ARM architectures prior to ARMv6 supported SWP and SWPB instructions that
- * atomically swap a 32-bit word for byte value between a register and a
- * memory location. From the ARMv6 architecture, ARM deprecates the use
- * of SWP and SWPB.
- */
-
-typedef uint8_t spinlock_t;
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * Name: up_testset
- *
- * Description:
- * Perform an atomic test and set operation on the provided spinlock.
- *
- * This function must be provided via the architecture-specific logic.
- *
- * Input Parameters:
- * lock - The address of spinlock object.
- *
- * Returned Value:
- * The spinlock is always locked upon return. The value of previous value
- * of the spinlock variable is returned, either SP_LOCKED if the spinlock
- * as previously locked (meaning that the test-and-set operation failed to
- * obtain the lock) or SP_UNLOCKED if the spinlock was previously unlocked
- * (meaning that we successfully obtained the lock)
- *
- ****************************************************************************/
-
-#if defined(CONFIG_ARCH_HAVE_TESTSET) &&
!defined(CONFIG_ARCH_HAVE_CUSTOM_TESTSET)
-static inline_function spinlock_t up_testset(volatile spinlock_t *lock)
-{
- spinlock_t ret = SP_UNLOCKED;
-
- __asm__ __volatile__
- (
- "1: \n"
- "ldrexb %0, [%2] \n"
- "cmp %0, %1 \n"
- "beq 2f \n"
- "strexb %0, %1, [%2] \n"
- "cmp %0, %1 \n"
- "beq 1b \n"
- "dmb \n"
- "2: \n"
- : "+r" (ret)
- : "r" (SP_LOCKED), "r" (lock)
- : "memory"
- );
-
- return ret;
-}
-#endif
-
-/* See prototype in nuttx/include/nuttx/spinlock.h */
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_ARM_INCLUDE_SPINLOCK_H */
diff --git a/arch/arm/src/common/CMakeLists.txt
b/arch/arm/src/common/CMakeLists.txt
index a7758eef7ae..177b4e68115 100644
--- a/arch/arm/src/common/CMakeLists.txt
+++ b/arch/arm/src/common/CMakeLists.txt
@@ -87,10 +87,6 @@ if(CONFIG_UNWINDER_ARM)
list(APPEND SRCS arm_backtrace_unwind.c)
endif()
-if(CONFIG_ARCH_HAVE_FETCHADD)
- list(APPEND SRCS ${ARCH_TOOLCHAIN_PATH}/arm_fetchadd.S)
-endif()
-
target_sources(arch PRIVATE ${SRCS})
nuttx_add_aux_library(STARTUP_OBJS crt0.c)
diff --git a/arch/arm/src/common/Make.defs b/arch/arm/src/common/Make.defs
index bec209f47b6..fb94089ee54 100644
--- a/arch/arm/src/common/Make.defs
+++ b/arch/arm/src/common/Make.defs
@@ -74,6 +74,3 @@ endif
CMN_ASRCS += fork.S
-ifeq ($(CONFIG_ARCH_HAVE_FETCHADD),y)
- CMN_ASRCS += arm_fetchadd.S
-endif
diff --git a/arch/arm/src/common/gnu/arm_fetchadd.S
b/arch/arm/src/common/gnu/arm_fetchadd.S
deleted file mode 100644
index 7435bb501ed..00000000000
--- a/arch/arm/src/common/gnu/arm_fetchadd.S
+++ /dev/null
@@ -1,269 +0,0 @@
-/****************************************************************************
- * arch/arm/src/common/gnu/arm_fetchadd.S
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements. See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership. The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#ifndef __ghs__
- .syntax unified
-#endif
- .file "arm_fetchadd.S"
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
- .text
-
-/****************************************************************************
- * Name: up_fetchadd32
- *
- * Description:
- * Perform an atomic fetch add operation on the provided 32-bit value.
- *
- * This function must be provided via the architecture-specific logic.
- *
- * Input Parameters:
- * addr - The address of 32-bit value to be incremented.
- * value - The 32-bit addend
- *
- * Returned Value:
- * The incremented value (volatile!)
- *
- ****************************************************************************/
-
- .globl up_fetchadd32
-#ifdef __ghs__
- .type up_fetchadd32, $function
-#else
- .type up_fetchadd32, %function
-#endif
-
-up_fetchadd32:
-
-1:
- ldrex r2, [r0] /* Fetch the value to
be incremented */
- add r2, r2, r1 /* Add the addend */
-
- strex r3, r2, [r0] /* Attempt to save the
result */
- teq r3, #0 /* r3 will be 1 if
strex failed */
- bne 1b /* Failed to lock...
try again */
-
- mov r0, r2 /* Return the
incremented value */
- bx lr /* Successful! */
- .size up_fetchadd32, . - up_fetchadd32
-
-/****************************************************************************
- * Name: up_fetchsub32
- *
- * Description:
- * Perform an atomic fetch subtract operation on the provided 32-bit value.
- *
- * This function must be provided via the architecture-specific logic.
- *
- * Input Parameters:
- * addr - The address of 32-bit value to be decremented.
- * value - The 32-bit subtrahend
- *
- * Returned Value:
- * The decremented value (volatile!)
- *
- ****************************************************************************/
-
- .globl up_fetchsub32
-#ifdef __ghs__
- .type up_fetchsub32, $function
-#else
- .type up_fetchsub32, %function
-#endif
-
-up_fetchsub32:
-
-1:
- ldrex r2, [r0] /* Fetch the value to
be decremented */
- sub r2, r2, r1 /* Subtract the
subtrahend */
-
- strex r3, r2, [r0] /* Attempt to save the
result */
- teq r3, #0 /* r3 will be 1 if
strex failed */
- bne 1b /* Failed to lock...
try again */
-
- mov r0, r2 /* Return the
decremented value */
- bx lr /* Successful! */
- .size up_fetchsub32, . - up_fetchsub32
-
-/****************************************************************************
- * Name: up_fetchadd16
- *
- * Description:
- * Perform an atomic fetch add operation on the provided 16-bit value.
- *
- * This function must be provided via the architecture-specific logic.
- *
- * Input Parameters:
- * addr - The address of 16-bit value to be incremented.
- * value - The 16-bit addend
- *
- * Returned Value:
- * The incremented value (volatile!)
- *
- ****************************************************************************/
-
- .globl up_fetchadd16
-#ifdef __ghs__
- .type up_fetchadd16, $function
-#else
- .type up_fetchadd16, %function
-#endif
-
-up_fetchadd16:
-
-1:
- ldrexh r2, [r0] /* Fetch the value to
be incremented */
- add r2, r2, r1 /* Add the addend */
-
- strexh r3, r2, [r0] /* Attempt to save the
result */
- teq r3, #0 /* r3 will be 1 if
strexh failed */
- bne 1b /* Failed to lock...
try again */
-
- mov r0, r2 /* Return the
incremented value */
- bx lr /* Successful! */
- .size up_fetchadd16, . - up_fetchadd16
-
-/****************************************************************************
- * Name: up_fetchsub16
- *
- * Description:
- * Perform an atomic fetch subtract operation on the provided 16-bit value.
- *
- * This function must be provided via the architecture-specific logic.
- *
- * Input Parameters:
- * addr - The address of 16-bit value to be decremented.
- * value - The 16-bit subtrahend
- *
- * Returned Value:
- * The decremented value (volatile!)
- *
- ****************************************************************************/
-
- .globl up_fetchsub16
-#ifdef __ghs__
- .type up_fetchsub16, $function
-#else
- .type up_fetchsub16, %function
-#endif
-
-up_fetchsub16:
-
-1:
- ldrexh r2, [r0] /* Fetch the value to
be decremented */
- sub r2, r2, r1 /* Subtract the
subtrahend */
-
- /* Attempt to save the decremented value */
-
- strexh r3, r2, [r0] /* Attempt to save the
result */
- teq r3, #0 /* r3 will be 1 if
strexh failed */
- bne 1b /* Failed to lock...
try again */
-
- mov r0, r2 /* Return the
decremented value */
- bx lr /* Successful! */
- .size up_fetchsub16, . - up_fetchsub16
-
-/****************************************************************************
- * Name: up_fetchadd8
- *
- * Description:
- * Perform an atomic fetch add operation on the provided 8-bit value.
- *
- * This function must be provided via the architecture-specific logic.
- *
- * Input Parameters:
- * addr - The address of 8-bit value to be incremented.
- * value - The 8-bit addend
- *
- * Returned Value:
- * The incremented value (volatile!)
- *
- ****************************************************************************/
-
- .globl up_fetchadd8
-#ifdef __ghs__
- .type up_fetchadd8, $function
-#else
- .type up_fetchadd8, %function
-#endif
-
-up_fetchadd8:
-
-1:
- ldrexb r2, [r0] /* Fetch the value to
be incremented */
- add r2, r2, r1 /* Add the addend */
-
- strexb r3, r2, [r0] /* Attempt to save the
result */
- teq r3, #0 /* r3 will be 1 if
strexb failed */
- bne 1b /* Failed to lock...
try again */
-
- mov r0, r2 /* Return the
incremented value */
- bx lr /* Successful! */
- .size up_fetchadd8, . - up_fetchadd8
-
-/****************************************************************************
- * Name: up_fetchsub8
- *
- * Description:
- * Perform an atomic fetch subtract operation on the provided 8-bit value.
- *
- * This function must be provided via the architecture-specific logic.
- *
- * Input Parameters:
- * addr - The address of 8-bit value to be decremented.
- * value - The 8-bit subtrahend
- *
- * Returned Value:
- * The decremented value (volatile!)
- *
- ****************************************************************************/
-
- .globl up_fetchsub8
-#ifdef __ghs__
- .type up_fetchsub8, $function
-#else
- .type up_fetchsub8, %function
-#endif
-
-up_fetchsub8:
-
-1:
- ldrexb r2, [r0] /* Fetch the value to
be decremented */
- sub r2, r2, r1 /* Subtract the
subtrahend */
-
- strexb r3, r2, [r0] /* Attempt to save the
result */
- teq r3, #0 /* r3 will be 1 if
strexb failed */
- bne 1b /* Failed to lock...
try again */
-
- mov r0, r2 /* Return the
decremented value */
- bx lr /* Successful! */
- .size up_fetchsub8, . - up_fetchsub8
- .end
diff --git a/arch/arm/src/common/iar/arm_fetchadd.S
b/arch/arm/src/common/iar/arm_fetchadd.S
deleted file mode 100644
index 1e78bb9832b..00000000000
--- a/arch/arm/src/common/iar/arm_fetchadd.S
+++ /dev/null
@@ -1,225 +0,0 @@
-/****************************************************************************
- * arch/arm/src/common/iar/arm_fetchadd.S
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements. See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership. The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
- MODULE up_testset
- SECTION .text:CODE:NOROOT(2)
-
-/****************************************************************************
- * Public Symbols
- ****************************************************************************/
-
- PUBLIC up_fetchadd32
- PUBLIC up_fetchsub32
- PUBLIC up_fetchadd16
- PUBLIC up_fetchsub16
- PUBLIC up_fetchadd8
- PUBLIC up_fetchsub8
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
- THUMB
-
-/****************************************************************************
- * Name: up_fetchadd32
- *
- * Description:
- * Perform an atomic fetch add operation on the provided 32-bit value.
- *
- * This function must be provided via the architecture-specific logic.
- *
- * Input Parameters:
- * addr - The address of 32-bit value to be incremented.
- * value - The 32-bit addend
- *
- * Returned Value:
- * The incremented value (volatile!)
- *
- ****************************************************************************/
-
-up_fetchadd32:
-
- ldrex r2, [r0] /* Fetch the value to
be incremented */
- add r2, r2, r1 /* Add the addend */
-
- strex r3, r2, [r0] /* Attempt to save the
result */
- teq r3, #0 /* r3 will be 1 if
strex failed */
- bne up_fetchadd32 /* Failed to lock...
try again */
-
- mov r0, r2 /* Return the
incremented value */
- bx lr /* Successful! */
-
-/****************************************************************************
- * Name: up_fetchsub32
- *
- * Description:
- * Perform an atomic fetch subtract operation on the provided 32-bit value.
- *
- * This function must be provided via the architecture-specific logic.
- *
- * Input Parameters:
- * addr - The address of 32-bit value to be decremented.
- * value - The 32-bit subtrahend
- *
- * Returned Value:
- * The decremented value (volatile!)
- *
- ****************************************************************************/
-
-up_fetchsub32:
-
- ldrex r2, [r0] /* Fetch the value to
be decremented */
- sub r2, r2, r1 /* Subtract the
subtrahend */
-
- strex r3, r2, [r0] /* Attempt to save the
result */
- teq r3, #0 /* r3 will be 1 if
strex failed */
- bne up_fetchsub32 /* Failed to lock...
try again */
-
- mov r0, r2 /* Return the
decremented value */
- bx lr /* Successful! */
-
-/****************************************************************************
- * Name: up_fetchadd16
- *
- * Description:
- * Perform an atomic fetch add operation on the provided 16-bit value.
- *
- * This function must be provided via the architecture-specific logic.
- *
- * Input Parameters:
- * addr - The address of 16-bit value to be incremented.
- * value - The 16-bit addend
- *
- * Returned Value:
- * The incremented value (volatile!)
- *
- ****************************************************************************/
-
-up_fetchadd16:
-
- ldrexh r2, [r0] /* Fetch the value to
be incremented */
- add r2, r2, r1 /* Add the addend */
-
- strexh r3, r2, [r0] /* Attempt to save the
result */
- teq r3, #0 /* r3 will be 1 if
strexh failed */
- bne up_fetchadd16 /* Failed to lock...
try again */
-
- mov r0, r2 /* Return the
incremented value */
- bx lr /* Successful! */
-
-/****************************************************************************
- * Name: up_fetchsub16
- *
- * Description:
- * Perform an atomic fetch subtract operation on the provided 16-bit value.
- *
- * This function must be provided via the architecture-specific logic.
- *
- * Input Parameters:
- * addr - The address of 16-bit value to be decremented.
- * value - The 16-bit subtrahend
- *
- * Returned Value:
- * The decremented value (volatile!)
- *
- ****************************************************************************/
-
-up_fetchsub16:
-
- ldrexh r2, [r0] /* Fetch the value to
be decremented */
- sub r2, r2, r1 /* Subtract the
subtrahend */
-
- /* Attempt to save the decremented value */
-
- strexh r3, r2, [r0] /* Attempt to save the
result */
- teq r3, #0 /* r3 will be 1 if
strexh failed */
- bne up_fetchsub16 /* Failed to lock...
try again */
-
- mov r0, r2 /* Return the
decremented value */
- bx lr /* Successful! */
-
-/****************************************************************************
- * Name: up_fetchadd8
- *
- * Description:
- * Perform an atomic fetch add operation on the provided 8-bit value.
- *
- * This function must be provided via the architecture-specific logic.
- *
- * Input Parameters:
- * addr - The address of 8-bit value to be incremented.
- * value - The 8-bit addend
- *
- * Returned Value:
- * The incremented value (volatile!)
- *
- ****************************************************************************/
-
-up_fetchadd8:
-
- ldrexb r2, [r0] /* Fetch the value to
be incremented */
- add r2, r2, r1 /* Add the addend */
-
- strexb r3, r2, [r0] /* Attempt to save the
result */
- teq r3, #0 /* r3 will be 1 if
strexb failed */
- bne up_fetchadd8 /* Failed to lock...
try again */
-
- mov r0, r2 /* Return the
incremented value */
- bx lr /* Successful! */
-
-/****************************************************************************
- * Name: up_fetchsub8
- *
- * Description:
- * Perform an atomic fetch subtract operation on the provided 8-bit value.
- *
- * This function must be provided via the architecture-specific logic.
- *
- * Input Parameters:
- * addr - The address of 8-bit value to be decremented.
- * value - The 8-bit subtrahend
- *
- * Returned Value:
- * The decremented value (volatile!)
- *
- ****************************************************************************/
-
-up_fetchsub8:
-
- ldrexb r2, [r0] /* Fetch the value to
be decremented */
- sub r2, r2, r1 /* Subtract the
subtrahend */
-
- strexb r3, r2, [r0] /* Attempt to save the
result */
- teq r3, #0 /* r3 will be 1 if
strexb failed */
- bne up_fetchsub8 /* Failed to lock...
try again */
-
- mov r0, r2 /* Return the
decremented value */
- bx lr /* Successful! */
-
- END
diff --git a/arch/arm/src/cxd56xx/CMakeLists.txt
b/arch/arm/src/cxd56xx/CMakeLists.txt
index f7bdb5aa9b7..051b9dc42a1 100644
--- a/arch/arm/src/cxd56xx/CMakeLists.txt
+++ b/arch/arm/src/cxd56xx/CMakeLists.txt
@@ -47,9 +47,6 @@ if(CONFIG_SMP)
list(APPEND SRCS cxd56_cpuidlestack.c)
list(APPEND SRCS cxd56_smpcall.c)
list(APPEND SRCS cxd56_cpustart.c)
- if(CONFIG_CXD56_TESTSET)
- list(APPEND SRCS cxd56_testset.c)
- endif()
endif()
if(CONFIG_ARCH_HAVE_MULTICPU)
diff --git a/arch/arm/src/cxd56xx/Kconfig b/arch/arm/src/cxd56xx/Kconfig
index f1cc8634117..4f66c7ba630 100644
--- a/arch/arm/src/cxd56xx/Kconfig
+++ b/arch/arm/src/cxd56xx/Kconfig
@@ -1414,21 +1414,6 @@ config CXD56_GEOFENCE
endif # CXD56_GNSS
-config CXD56_TESTSET
- bool "Use custom testset for spinlock"
- default y
- depends on SMP
- ---help---
- Use custom testset
-
-if CXD56_TESTSET
-
-config CXD56_TESTSET_WITH_HWSEM
- bool "Use custom testset based on hardware semaphore"
- default !CXD56_USE_SYSBUS
-
-endif # CXD56_TESTSET
-
config CXD56_ATOMIC_WITH_HWSEM
bool "Use atomic based on hardware semaphore"
default !CXD56_USE_SYSBUS
diff --git a/arch/arm/src/cxd56xx/Make.defs b/arch/arm/src/cxd56xx/Make.defs
index 04e9ee59d01..23cf0810eca 100644
--- a/arch/arm/src/cxd56xx/Make.defs
+++ b/arch/arm/src/cxd56xx/Make.defs
@@ -46,10 +46,6 @@ ifeq ($(CONFIG_SMP),y)
CHIP_CSRCS += cxd56_cpuidlestack.c
CHIP_CSRCS += cxd56_smpcall.c
CHIP_CSRCS += cxd56_cpustart.c
-ifeq ($(CONFIG_CXD56_TESTSET),y)
-CHIP_CSRCS += cxd56_testset.c
-CMN_ASRCS := $(filter-out arm_testset.S,$(CMN_ASRCS))
-endif
endif
ifeq ($(CONFIG_ARCH_HAVE_MULTICPU),y)
diff --git a/arch/arm/src/cxd56xx/cxd56_atomic.c
b/arch/arm/src/cxd56xx/cxd56_atomic.c
index 2736b3fd9de..198de874340 100644
--- a/arch/arm/src/cxd56xx/cxd56_atomic.c
+++ b/arch/arm/src/cxd56xx/cxd56_atomic.c
@@ -30,7 +30,7 @@
* Pre-processor Definitions
****************************************************************************/
-#define SPH_SMP 13
+#define SPH_SMP 14
/****************************************************************************
* Public Data
diff --git a/arch/arm/src/cxd56xx/cxd56_sph.c b/arch/arm/src/cxd56xx/cxd56_sph.c
index 3b3f9bb0acf..4c706fca167 100644
--- a/arch/arm/src/cxd56xx/cxd56_sph.c
+++ b/arch/arm/src/cxd56xx/cxd56_sph.c
@@ -270,11 +270,9 @@ int cxd56_sphinitialize(const char *devname)
int ret;
int i;
- /* No. 0-2 and (13)-15 semaphores are reserved by other system. */
+ /* No. 0-2 and (14)-15 semaphores are reserved by other system. */
-#if defined(CONFIG_CXD56_ATOMIC_WITH_HWSEM)
- for (i = 3; i < 13; i++)
-#elif defined(CONFIG_CXD56_TESTSET_WITH_HWSEM)
+#ifdef CONFIG_CXD56_ATOMIC_WITH_HWSEM
for (i = 3; i < 14; i++)
#else
for (i = 3; i < 15; i++)
diff --git a/arch/arm/src/cxd56xx/cxd56_testset.c
b/arch/arm/src/cxd56xx/cxd56_testset.c
deleted file mode 100644
index 936f3006977..00000000000
--- a/arch/arm/src/cxd56xx/cxd56_testset.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/****************************************************************************
- * arch/arm/src/cxd56xx/cxd56_testset.c
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements. See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership. The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#include <nuttx/arch.h>
-#include <nuttx/spinlock.h>
-
-#include "hardware/cxd56_sph.h"
-#include "cxd56_sph.h"
-#include "arm_internal.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-#define SPH_SMP 14 /* Use hardware semaphore #14 */
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: up_testset2
- ****************************************************************************/
-
-spinlock_t up_testset2(volatile spinlock_t *lock)
-{
- register uintptr_t ret asm("r0") = (uintptr_t)(lock);
-
- asm volatile (
- "mov r1, #1 \n"
- "1: \n"
- "ldrexb r2, [%0] \n"
- "cmp r2, r1 \n"
- "beq 2f \n"
- "strexb r2, r1, [%0] \n"
- "cmp r2, r1 \n"
- "beq 1b \n"
- "dmb \n"
- "mov %0, #0 \n"
- "bx lr \n"
- "2: \n"
- "strexb r2, r1, [%0] \n" /* dummy strex to release */
- "mov %0, #1 \n"
- : "+r" (ret)
- :
- : "r1", "r2");
-
- return ret;
-}
-
-/****************************************************************************
- * Name: up_testset
- *
- * Description:
- * Perform an atomic test and set operation on the provided spinlock.
- * This function must be provided via the architecture-specific logic.
- *
- * Input Parameters:
- * lock - A reference to the spinlock object.
- *
- * Returned Value:
- * The spinlock is always locked upon return. The previous value of the
- * spinlock variable is returned, either SP_LOCKED if the spinlock was
- * previously locked (meaning that the test-and-set operation failed to
- * obtain the lock) or SP_UNLOCKED if the spinlock was previously unlocked
- * (meaning that we successfully obtained the lock).
- *
- ****************************************************************************/
-
-spinlock_t up_testset(volatile spinlock_t *lock)
-{
-#ifdef CONFIG_CXD56_TESTSET_WITH_HWSEM
- spinlock_t ret;
- uint32_t sphlocked = ((this_cpu() + 2) << 16) | 0x1;
-
- /* Lock hardware semaphore */
-
- do
- {
- putreg32(REQ_LOCK, CXD56_SPH_REQ(SPH_SMP));
- }
- while (getreg32(CXD56_SPH_STS(SPH_SMP)) != sphlocked);
-
- ret = *lock;
-
- if (ret == SP_UNLOCKED)
- {
- *lock = SP_LOCKED;
- UP_DMB();
- }
-
- /* Unlock hardware semaphore */
-
- putreg32(REQ_UNLOCK, CXD56_SPH_REQ(SPH_SMP));
-#else
- spinlock_t ret = up_testset2(lock);
-#endif
-
- return ret;
-}
diff --git a/arch/arm/src/lc823450/Make.defs b/arch/arm/src/lc823450/Make.defs
index acff774bee0..73dc211fc94 100644
--- a/arch/arm/src/lc823450/Make.defs
+++ b/arch/arm/src/lc823450/Make.defs
@@ -96,8 +96,6 @@ ifeq ($(CONFIG_SMP),y)
CHIP_CSRCS += lc823450_cpuidlestack.c
CHIP_CSRCS += lc823450_smpcall.c
CHIP_CSRCS += lc823450_cpustart.c
-CHIP_CSRCS += lc823450_testset.c
-CMN_ASRCS := $(filter-out arm_testset.S,$(CMN_ASRCS))
endif
ifeq ($(CONFIG_ARCH_HAVE_MULTICPU),y)
diff --git a/arch/arm/src/lc823450/lc823450_testset.c
b/arch/arm/src/lc823450/lc823450_testset.c
deleted file mode 100644
index 38c57fac9a9..00000000000
--- a/arch/arm/src/lc823450/lc823450_testset.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/****************************************************************************
- * arch/arm/src/lc823450/lc823450_testset.c
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements. See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership. The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#include <nuttx/arch.h>
-#include <nuttx/spinlock.h>
-
-#include "arm_internal.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-#define LC823450_MUTEX_REG_BASE 0x40005000
-#define MUTEX_REG_MUTEX0 (LC823450_MUTEX_REG_BASE + 0x00)
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: up_testset
- *
- * Description:
- * Perform and atomic test and set operation on the provided spinlock.
- *
- * This function must be provided via the architecture-specific logic.
- *
- * Note:
- * LC823450 does not support ldrex/strex. Instead, MUTEX is provided.
- *
- * Input Parameters:
- * lock - A reference to the spinlock object.
- *
- * Returned Value:
- * The spinlock is always locked upon return. The previous value of the
- * spinlock variable is returned, either SP_LOCKED if the spinlock was
- * previously locked (meaning that the test-and-set operation failed to
- * obtain the lock) or SP_UNLOCKED if the spinlock was previously unlocked
- * (meaning that we successfully obtained the lock).
- *
- ****************************************************************************/
-
-spinlock_t up_testset(volatile spinlock_t *lock)
-{
- uint32_t val;
- spinlock_t ret;
- irqstate_t flags;
-
- flags = up_irq_save();
-
- val = (this_cpu() << 16) | 0x1;
-
- do
- {
- putreg32(val, MUTEX_REG_MUTEX0);
- }
- while (getreg32(MUTEX_REG_MUTEX0) != val);
-
- UP_DMB();
-
- ret = *lock;
-
- if (ret == SP_UNLOCKED)
- {
- *lock = SP_LOCKED;
- }
-
- UP_DMB();
-
- val = (this_cpu() << 16) | 0x0;
- putreg32(val, MUTEX_REG_MUTEX0);
-
- up_irq_restore(flags);
-
- return ret;
-}
diff --git a/arch/arm/src/rp2040/CMakeLists.txt
b/arch/arm/src/rp2040/CMakeLists.txt
index ff4f0e8657a..5d70f588178 100644
--- a/arch/arm/src/rp2040/CMakeLists.txt
+++ b/arch/arm/src/rp2040/CMakeLists.txt
@@ -36,8 +36,7 @@ list(
rp2040_pll.c)
if(CONFIG_SMP)
- list(APPEND SRCS rp2040_cpustart.c rp2040_smpcall.c rp2040_cpuidlestack.c
- rp2040_testset.c)
+ list(APPEND SRCS rp2040_cpustart.c rp2040_smpcall.c rp2040_cpuidlestack.c)
endif()
if(CONFIG_ARCH_HAVE_MULTICPU)
diff --git a/arch/arm/src/rp2040/Make.defs b/arch/arm/src/rp2040/Make.defs
index f617f2d6d0d..a3ac3780095 100644
--- a/arch/arm/src/rp2040/Make.defs
+++ b/arch/arm/src/rp2040/Make.defs
@@ -41,8 +41,6 @@ ifeq ($(CONFIG_SMP),y)
CHIP_CSRCS += rp2040_cpustart.c
CHIP_CSRCS += rp2040_smpcall.c
CHIP_CSRCS += rp2040_cpuidlestack.c
-CHIP_CSRCS += rp2040_testset.c
-CMN_ASRCS := $(filter-out arm_testset.S,$(CMN_ASRCS))
endif
ifeq ($(CONFIG_ARCH_HAVE_MULTICPU),y)
diff --git a/arch/arm/src/rp2040/rp2040_testset.c
b/arch/arm/src/rp2040/rp2040_testset.c
deleted file mode 100644
index bfe8af5d446..00000000000
--- a/arch/arm/src/rp2040/rp2040_testset.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/****************************************************************************
- * arch/arm/src/rp2040/rp2040_testset.c
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements. See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership. The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#include <nuttx/arch.h>
-#include <nuttx/spinlock.h>
-
-#include "hardware/rp2040_sio.h"
-#include "arm_internal.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-#define RP2040_TESTSET_SPINLOCK 0 /* Spinlock used for test and set */
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: up_testset
- *
- * Description:
- * Perform and atomic test and set operation on the provided spinlock.
- * This function must be provided via the architecture-specific logic.
- *
- * Input Parameters:
- * lock - A reference to the spinlock object.
- *
- * Returned Value:
- * The spinlock is always locked upon return. The previous value of the
- * spinlock variable is returned, either SP_LOCKED if the spinlock was
- * previously locked (meaning that the test-and-set operation failed to
- * obtain the lock) or SP_UNLOCKED if the spinlock was previously unlocked
- * (meaning that we successfully obtained the lock).
- *
- ****************************************************************************/
-
-spinlock_t up_testset(volatile spinlock_t *lock)
-{
- spinlock_t ret;
-
- /* Lock hardware spinlock */
-
- while (getreg32(RP2040_SIO_SPINLOCK(RP2040_TESTSET_SPINLOCK)) == 0)
- ;
-
- ret = *lock;
-
- if (ret == SP_UNLOCKED)
- {
- *lock = SP_LOCKED;
- UP_DMB();
- }
-
- /* Unlock hardware spinlock */
-
- putreg32(0, RP2040_SIO_SPINLOCK(RP2040_TESTSET_SPINLOCK));
-
- return ret;
-}
diff --git a/arch/arm/src/rp23xx/CMakeLists.txt
b/arch/arm/src/rp23xx/CMakeLists.txt
index 0fb295a4966..84c46b22374 100644
--- a/arch/arm/src/rp23xx/CMakeLists.txt
+++ b/arch/arm/src/rp23xx/CMakeLists.txt
@@ -36,8 +36,7 @@ list(
rp23xx_pll.c)
if(CONFIG_SMP)
- list(APPEND SRCS rp23xx_cpustart.c rp23xx_smpcall.c rp23xx_cpuidlestack.c
- rp23xx_testset.c)
+ list(APPEND SRCS rp23xx_cpustart.c rp23xx_smpcall.c rp23xx_cpuidlestack.c)
endif()
if(CONFIG_ARCH_HAVE_MULTICPU)
diff --git a/arch/arm/src/rp23xx/Make.defs b/arch/arm/src/rp23xx/Make.defs
index 3fbd4b32e46..1efbfeaabb3 100644
--- a/arch/arm/src/rp23xx/Make.defs
+++ b/arch/arm/src/rp23xx/Make.defs
@@ -40,8 +40,6 @@ ifeq ($(CONFIG_SMP),y)
CHIP_CSRCS += rp23xx_cpustart.c
CHIP_CSRCS += rp23xx_smpcall.c
CHIP_CSRCS += rp23xx_cpuidlestack.c
-CHIP_CSRCS += rp23xx_testset.c
-CMN_ASRCS := $(filter-out arm_testset.S,$(CMN_ASRCS))
endif
ifeq ($(CONFIG_ARCH_HAVE_MULTICPU),y)
diff --git a/arch/arm/src/rp23xx/rp23xx_testset.c
b/arch/arm/src/rp23xx/rp23xx_testset.c
deleted file mode 100644
index 1048c4276d5..00000000000
--- a/arch/arm/src/rp23xx/rp23xx_testset.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/****************************************************************************
- * arch/arm/src/rp23xx/rp23xx_testset.c
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements. See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership. The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#include <nuttx/arch.h>
-#include <nuttx/spinlock.h>
-
-#include "hardware/rp23xx_sio.h"
-#include "arm_internal.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* Errata RP2350-E2 SIO SPINLOCK writes are mirrored at +0x80 offset
- * Use only safe SPINLOCKS
- * The following SIO spinlocks can be used normally as they do not alias
- * with writable registers: 5, 6, 7, 10,11, and 18 through 31.
- */
-
-#define RP23XX_TESTSET_SPINLOCK 7 /* Spinlock used for test and set */
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: up_testset
- *
- * Description:
- * Perform and atomic test and set operation on the provided spinlock.
- * This function must be provided via the architecture-specific logic.
- *
- * Input Parameters:
- * lock - A reference to the spinlock object.
- *
- * Returned Value:
- * The spinlock is always locked upon return. The previous value of the
- * spinlock variable is returned, either SP_LOCKED if the spinlock was
- * previously locked (meaning that the test-and-set operation failed to
- * obtain the lock) or SP_UNLOCKED if the spinlock was previously unlocked
- * (meaning that we successfully obtained the lock).
- *
- ****************************************************************************/
-
-spinlock_t up_testset(volatile spinlock_t *lock)
-{
- spinlock_t ret;
-
- /* Lock hardware spinlock */
-
- while (getreg32(RP23XX_SIO_SPINLOCK(RP23XX_TESTSET_SPINLOCK)) == 0)
- ;
-
- ret = *lock;
-
- if (ret == SP_UNLOCKED)
- {
- *lock = SP_LOCKED;
- UP_DMB();
- }
-
- /* Unlock hardware spinlock */
-
- putreg32(0, RP23XX_SIO_SPINLOCK(RP23XX_TESTSET_SPINLOCK));
-
- return ret;
-}
diff --git a/arch/arm/src/s32k1xx/Kconfig b/arch/arm/src/s32k1xx/Kconfig
index 496e2877877..4cb4f317c39 100644
--- a/arch/arm/src/s32k1xx/Kconfig
+++ b/arch/arm/src/s32k1xx/Kconfig
@@ -81,7 +81,6 @@ config ARCH_CHIP_S32K14X
bool
select ARCH_CORTEXM4
select ARCH_HAVE_FPU
- select ARCH_HAVE_FETCHADD
select S32K1XX_HAVE_EWM
select S32K1XX_HAVE_FTM2
select S32K1XX_HAVE_FTM3
diff --git a/arch/arm/src/s32k3xx/Kconfig b/arch/arm/src/s32k3xx/Kconfig
index 2c15d6b8ee1..84adf6eb848 100644
--- a/arch/arm/src/s32k3xx/Kconfig
+++ b/arch/arm/src/s32k3xx/Kconfig
@@ -174,7 +174,6 @@ config ARCH_FAMILY_S32K3XX_BASE
bool
select ARCH_CORTEXM7
select ARCH_HAVE_FPU
- select ARCH_HAVE_FETCHADD
select ARMV7M_HAVE_ICACHE
select ARMV7M_HAVE_DCACHE
select ARMV7M_HAVE_ITCM
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 84b3c1dfe03..9de3bb3f4c6 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -163,7 +163,7 @@ config ARCH_CHIP_BCM2711
select ARCH_HAVE_IRQTRIGGER
select ARCH_NEED_ADDRENV_MAPPING
select ARCH_HAVE_MULTICPU
- select ARCH_USE_MMU # Required for up_testset
+ select ARCH_USE_MMU
select ARMV8A_HAVE_GICv2
select ARCH_HAVE_SDIO
select ARCH_HAVE_IRQPRIO
@@ -322,7 +322,6 @@ config ARCH_CORTEX_A53
select ARCH_ICACHE
select ARCH_HAVE_MMU
select ARCH_HAVE_FPU
- select ARCH_HAVE_TESTSET
select ARM64_HAVE_NEON
config ARCH_CORTEX_A55
@@ -334,7 +333,6 @@ config ARCH_CORTEX_A55
select ARCH_ICACHE
select ARCH_HAVE_MMU
select ARCH_HAVE_FPU
- select ARCH_HAVE_TESTSET
select ARM64_HAVE_NEON
config ARCH_CORTEX_A57
@@ -346,7 +344,6 @@ config ARCH_CORTEX_A57
select ARCH_ICACHE
select ARCH_HAVE_MMU
select ARCH_HAVE_FPU
- select ARCH_HAVE_TESTSET
select ARM64_HAVE_NEON
config ARCH_CORTEX_A72
@@ -358,7 +355,6 @@ config ARCH_CORTEX_A72
select ARCH_ICACHE
select ARCH_HAVE_MMU
select ARCH_HAVE_FPU
- select ARCH_HAVE_TESTSET
select ARM64_HAVE_NEON
config ARCH_CORTEX_R82
@@ -371,7 +367,6 @@ config ARCH_CORTEX_R82
select ARCH_HAVE_MPU
select ARCH_HAVE_FPU
select ARCH_HAVE_CLUSTER_PMU
- select ARCH_HAVE_TESTSET
select ARM64_HAVE_NEON
select ARCH_HAVE_PERF_EVENTS_USER_ACCESS if !ARCH_CLUSTER_PMU
@@ -385,7 +380,6 @@ config ARCH_CPU_UNKNOWN
select ARCH_ICACHE
select ARCH_HAVE_MMU
select ARCH_HAVE_FPU
- select ARCH_HAVE_TESTSET
select ARM64_HAVE_NEON
config ARCH_FAMILY
diff --git a/arch/arm64/include/arch.h b/arch/arm64/include/arch.h
index 59f83f69b65..4f0288e67db 100644
--- a/arch/arm64/include/arch.h
+++ b/arch/arm64/include/arch.h
@@ -39,6 +39,7 @@
#endif
#include <nuttx/irq.h>
+#include <arch/barriers.h>
/****************************************************************************
* Pre-processor Prototypes
@@ -53,6 +54,9 @@
#endif /* CONFIG_ARCH_ADDRENV */
+#define UP_WFE() __asm__ __volatile__ ("wfe" : : : "memory")
+#define UP_SEV() __asm__ __volatile__ ("sev" : : : "memory")
+
/****************************************************************************
* Inline functions
****************************************************************************/
diff --git a/arch/arm64/include/spinlock.h b/arch/arm64/include/spinlock.h
deleted file mode 100644
index 3531e2a1057..00000000000
--- a/arch/arm64/include/spinlock.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/****************************************************************************
- * arch/arm64/include/spinlock.h
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements. See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership. The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-#ifndef __ARCH_ARM64_INCLUDE_SPINLOCK_H
-#define __ARCH_ARM64_INCLUDE_SPINLOCK_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-# include <stdint.h>
-#endif /* __ASSEMBLY__ */
-
-#include <arch/barriers.h>
-
-/****************************************************************************
- * Pre-processor Prototypes
- ****************************************************************************/
-
-/* Spinlock states */
-
-#define SP_UNLOCKED 0 /* The Un-locked state */
-#define SP_LOCKED 1 /* The Locked state */
-
-/* Memory barriers for use with NuttX spinlock logic
- *
- * Data Memory Barrier (DMB) acts as a memory barrier. It ensures that all
- * explicit memory accesses that appear in program order before the DMB
- * instruction are observed before any explicit memory accesses that appear
- * in program order after the DMB instruction. It does not affect the
- * ordering of any other instructions executing on the processor
- *
- * dmb st - Data memory barrier. Wait for stores to complete.
- *
- * Data Synchronization Barrier (DSB) acts as a special kind of memory
- * barrier. No instruction in program order after this instruction executes
- * until this instruction completes. This instruction completes when: (1) All
- * explicit memory accesses before this instruction complete, and (2) all
- * Cache, Branch predictor and TLB maintenance operations before this
- * instruction complete.
- *
- * dsb sy - Data synchronization barrier. Assures that the CPU waits until
- * all memory accesses are complete
- */
-
-#define UP_WFE() __asm__ __volatile__ ("wfe" : : : "memory")
-#define UP_SEV() __asm__ __volatile__ ("sev" : : : "memory")
-
-#ifndef __ASSEMBLY__
-
-/* The Type of a spinlock.
- * ARM official document
- * ARM® Cortex®-A Series, Version: 1.0, Programmer’s Guide for ARMv8-A
- * ARM DEN0024A (ID050815)
- *
- * chapter 14.1.4 Synchronization
- *
- * The A64 instruction set has instructions for implementing
- * synchronization functions:
- * -- Load Exclusive (LDXR): LDXR W|Xt, [Xn]
- * -- Store Exclusive (STXR): STXR Ws, W|Xt, [Xn] where Ws
- * indicates whether the store completed successfully.
- * 0 = success.
- * -- Clear Exclusive access monitor (CLREX) This is used to
- * clear the state of the Local Exclusive Monitor.
- */
-
-typedef uint64_t spinlock_t;
-
-#if defined(CONFIG_ARCH_HAVE_TESTSET)
-static inline_function spinlock_t up_testset(volatile spinlock_t *lock)
-{
- spinlock_t ret = SP_LOCKED;
- spinlock_t tmp = 0;
-
- __asm__ __volatile__
- (
- "1: \n"
- "ldaxr %0, [%3] \n"
- "cmp %0, %2 \n"
- "beq 2f \n"
- "stxr %w1, %2, [%3] \n"
- "cbnz %w1, 1b \n"
- "2: \n"
- : "=r" (ret)
- : "r" (tmp), "r" (SP_LOCKED), "r" (lock)
- : "memory"
- );
-
- return ret;
-}
-#endif
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_ARM64_INCLUDE_SPINLOCK_H */
diff --git a/arch/ceva/include/arch.h b/arch/ceva/include/arch.h
index cad0d814b19..e1371c1cbc9 100644
--- a/arch/ceva/include/arch.h
+++ b/arch/ceva/include/arch.h
@@ -34,6 +34,7 @@
#include <nuttx/config.h>
#include <arch/chip/chip.h>
+#include <arch/barriers.h>
/****************************************************************************
* Pre-processor Definitions
diff --git a/arch/ceva/include/spinlock.h b/arch/ceva/include/spinlock.h
deleted file mode 100644
index dbdb6e1dd6e..00000000000
--- a/arch/ceva/include/spinlock.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/****************************************************************************
- * arch/ceva/include/spinlock.h
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements. See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership. The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-#ifndef __ARCH_CEVA_INCLUDE_SPINLOCK_H
-#define __ARCH_CEVA_INCLUDE_SPINLOCK_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-# include <stdint.h>
-#endif /* __ASSEMBLY__ */
-
-#if defined(CONFIG_ARCH_XC5)
-# include <arch/xc5/spinlock.h>
-#elif defined(CONFIG_ARCH_XM6)
-# include <arch/xm6/spinlock.h>
-#endif
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* Spinlock states */
-
-#define SP_UNLOCKED 0 /* The Unlocked state */
-#define SP_LOCKED 1 /* The Locked state */
-
-/* Memory barriers for use with NuttX spinlock logic
- *
- * Data Memory Barrier (DMB) acts as a memory barrier. It ensures that all
- * explicit memory accesses that appear in program order before the DMB
- * instruction are observed before any explicit memory accesses that appear
- * in program order after the DMB instruction. It does not affect the
- * ordering of any other instructions executing on the processor
- *
- * Data Synchronization Barrier (DSB) acts as a special kind of memory
- * barrier. No instruction in program order after this instruction executes
- * until this instruction completes. This instruction completes when: (1) All
- * explicit memory accesses before this instruction complete, and (2) all
- * Cache, Branch predictor and TLB maintenance operations before this
- * instruction complete.
- *
- */
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/* The Type of a spinlock. */
-
-typedef uint32_t spinlock_t;
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * Name: up_testset
- *
- * Description:
- * Perform an atomic test and set operation on the provided spinlock.
- *
- * This function must be provided via the architecture-specific logic.
- *
- * Input Parameters:
- * lock - The address of spinlock object.
- *
- * Returned Value:
- * The spinlock is always locked upon return. The value of previous value
- * of the spinlock variable is returned, either SP_LOCKED if the spinlock
- * as previously locked (meaning that the test-and-set operation failed to
- * obtain the lock) or SP_UNLOCKED if the spinlock was previously unlocked
- * (meaning that we successfully obtained the lock)
- *
- ****************************************************************************/
-
-/* See prototype in nuttx/include/nuttx/spinlock.h */
-
-/* Include CEVA architecture-specific spinlock definitions */
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_CEVA_INCLUDE_SPINLOCK_H */
diff --git a/arch/ceva/include/xc5/spinlock.h b/arch/ceva/include/xc5/spinlock.h
deleted file mode 100644
index c60a2882170..00000000000
--- a/arch/ceva/include/xc5/spinlock.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/****************************************************************************
- * arch/ceva/include/xc5/spinlock.h
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements. See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership. The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-#ifndef __ARCH_CEVA_INCLUDE_XC5_SPINLOCK_H
-#define __ARCH_CEVA_INCLUDE_XC5_SPINLOCK_H
-
-/****************************************************************************
- * Inline functions
- ****************************************************************************/
-
-#endif /* __ARCH_CEVA_INCLUDE_XC5_SPINLOCK_H */
diff --git a/arch/ceva/include/xm6/spinlock.h b/arch/ceva/include/xm6/spinlock.h
deleted file mode 100644
index 4fbfb70c3ec..00000000000
--- a/arch/ceva/include/xm6/spinlock.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/****************************************************************************
- * arch/ceva/include/xm6/spinlock.h
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements. See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership. The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-#ifndef __ARCH_CEVA_INCLUDE_XM6_SPINLOCK_H
-#define __ARCH_CEVA_INCLUDE_XM6_SPINLOCK_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <arch/xm6/irq.h>
-#include <arch/xm6/barriers.h>
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-#define SP_SECTION __attribute__ ((section(".DSECT spinlock")))
-
-/****************************************************************************
- * Inline functions
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/****************************************************************************
- * Name: up_testset
- *
- * Description:
- * Perform an atomic test and set operation on the provided spinlock.
- *
- * This function must be provided via the architecture-specific logic.
- *
- * Input Parameters:
- * lock - The address of spinlock object.
- *
- * Returned Value:
- * The spinlock is always locked upon return. The value of previous value
- * of the spinlock variable is returned, either SP_LOCKED if the spinlock
- * as previously locked (meaning that the test-and-set operation failed to
- * obtain the lock) or SP_UNLOCKED if the spinlock was previously unlocked
- * (meaning that we successfully obtained the lock)
- *
- ****************************************************************************/
-
-static inline spinlock_t up_testset(volatile spinlock_t *lock)
-{
- irqstate_t flags;
- spinlock_t old;
-
- /* Disable the interrupt */
-
- flags = up_irq_save();
-
- while (1)
- {
- uint32_t modc = 0;
-
- /* Issue exclusive read */
-
- __asm__ __volatile__
- (
- "nop\n"
- "LS0.ld (%1.ui).ui, %0.ui || monitor {on}\n"
- "nop #0x02"
- : "=r"(old)
- : "r"(lock)
- );
-
- /* Is it already locked by other? */
-
- if (old == SP_LOCKED)
- {
- break; /* Yes, exit */
- }
-
- /* Not yet, issue exclusive write */
-
- __asm__ __volatile__
- (
- "LS1.st %2.ui, (%1.ui).ui || monitor {off}\n"
- "mov modc.ui, %0.ui\n"
- "nop"
- : "=r"(modc)
- : "r"(lock), "r"(SP_LOCKED)
- : "memory"
- );
-
- /* Exclusive write success? */
-
- if ((modc & 0x01) == 0) /* Bit[0] Monitor status */
- {
- break; /* Yes, we are done */
- }
-
- /* Fail, let's try again */
- }
-
- /* Restore the interrupt */
-
- up_irq_restore(flags);
-
- return old;
-}
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __ARCH_CEVA_INCLUDE_XM6_SPINLOCK_H */
diff --git a/arch/risc-v/Kconfig b/arch/risc-v/Kconfig
index d3849635da6..8ca23643063 100644
--- a/arch/risc-v/Kconfig
+++ b/arch/risc-v/Kconfig
@@ -32,7 +32,6 @@ config ARCH_CHIP_K210
select ARCH_HAVE_FPU
select ARCH_HAVE_DPFPU
select ARCH_HAVE_MPU
- select ARCH_HAVE_TESTSET
select ARCH_HAVE_MULTICPU
select ARCH_HAVE_MISALIGN_EXCEPTION
select ONESHOT
@@ -526,7 +525,6 @@ config ARCH_RV_ISA_M
config ARCH_RV_ISA_A
bool
default n
- select ARCH_HAVE_TESTSET
config ARCH_RV_ISA_C
bool
diff --git a/arch/risc-v/include/arch.h b/arch/risc-v/include/arch.h
index 16d1f89ee63..b7a373546c4 100644
--- a/arch/risc-v/include/arch.h
+++ b/arch/risc-v/include/arch.h
@@ -38,6 +38,8 @@
# include <stddef.h>
#endif
+#include <arch/barriers.h>
+
/****************************************************************************
* Pre-processor Prototypes
****************************************************************************/
diff --git a/arch/risc-v/include/spinlock.h b/arch/risc-v/include/spinlock.h
deleted file mode 100644
index f7ca3120a0f..00000000000
--- a/arch/risc-v/include/spinlock.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/****************************************************************************
- * arch/risc-v/include/spinlock.h
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements. See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership. The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-#ifndef __ARCH_RISCV_INCLUDE_SPINLOCK_H
-#define __ARCH_RISCV_INCLUDE_SPINLOCK_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-# include <stdint.h>
-#endif /* __ASSEMBLY__ */
-
-#include <arch/barriers.h>
-
-/* Include RISC-V architecture-specific IRQ definitions (including register
- * save structure and up_irq_save()/up_irq_restore() functions)
- */
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* Spinlock states */
-
-#define SP_UNLOCKED 0 /* The Un-locked state */
-#define SP_LOCKED 1 /* The Locked state */
-
-/* Memory barriers for use with NuttX spinlock logic
- *
- * Data Memory Barrier (DMB) acts as a memory barrier. It ensures that all
- * explicit memory accesses that appear in program order before the DMB
- * instruction are observed before any explicit memory accesses that appear
- * in program order after the DMB instruction. It does not affect the
- * ordering of any other instructions executing on the processor
- *
- * Data Synchronization Barrier (DSB) acts as a special kind of memory
- * barrier. No instruction in program order after this instruction executes
- * until this instruction completes. This instruction completes when: (1) All
- * explicit memory accesses before this instruction complete, and (2) all
- * Cache, Branch predictor and TLB maintenance operations before this
- * instruction complete.
- *
- */
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/* The Type of a spinlock.
- *
- * RISC-V architecture (in the standard atomic-instruction extension "A")
- * supports exclusive accesses to memory locations in the form of the
- * Load-Reserved (LR), Store-Conditional (SC) and Atomic Memory Operations
- * (AMO) instructions. For LR and SC, RV64 supports doubleword aligned data
- * only but others supports word aligned data. For AMO, word and doubleword
- * alignments are accepted.
- *
- * RISC-V architecture supports fence instruction to ensure memory ordering.
- */
-
-typedef uintptr_t spinlock_t;
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * Name: up_testset
- *
- * Description:
- * Perform an atomic test and set operation on the provided spinlock.
- *
- * This function must be provided via the architecture-specific logic.
- *
- * Input Parameters:
- * lock - The address of spinlock object.
- *
- * Returned Value:
- * The spinlock is always locked upon return. The value of previous value
- * of the spinlock variable is returned, either SP_LOCKED if the spinlock
- * as previously locked (meaning that the test-and-set operation failed to
- * obtain the lock) or SP_UNLOCKED if the spinlock was previously unlocked
- * (meaning that we successfully obtained the lock)
- *
- ****************************************************************************/
-
-#if defined(CONFIG_ARCH_RV_ISA_A)
-static inline_function spinlock_t up_testset(volatile spinlock_t *lock)
-{
- spinlock_t ret = SP_LOCKED;
-
- __asm__ __volatile__
- (
-#ifdef CONFIG_ARCH_RV32
- "amoswap.w %0, %0, %1\n"
-#else
- "amoswap.d %0, %0, %1\n"
-#endif
- "fence\n"
- : "+r" (ret), "+A" (*lock)
- :
- : "memory"
- );
-
- return ret;
-}
-#endif
-
-/* See prototype in nuttx/include/nuttx/spinlock.h */
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_RISCV_INCLUDE_SPINLOCK_H */
diff --git a/arch/sim/include/spinlock.h b/arch/sim/include/spinlock.h
deleted file mode 100644
index 33aebd4ad7c..00000000000
--- a/arch/sim/include/spinlock.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/****************************************************************************
- * arch/sim/include/spinlock.h
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements. See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership. The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-#ifndef __ARCH_SIM_INCLUDE_SPINLOCK_H
-#define __ARCH_SIM_INCLUDE_SPINLOCK_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <stdint.h>
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* Must match definitions in up_testset.c */
-
-#define SP_UNLOCKED 0 /* The Un-locked state */
-#define SP_LOCKED 1 /* The Locked state */
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-/* Must match definitions in up_testset.c */
-
-typedef uint8_t spinlock_t;
-
-/****************************************************************************
- * Public Functions Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * Name: up_testset
- *
- * Description:
- * Perform an atomic test and set operation on the provided spinlock.
- *
- * This function must be provided via the architecture-specific logic.
- *
- * Input Parameters:
- * lock - The address of spinlock object.
- *
- * Returned Value:
- * The spinlock is always locked upon return. The value of previous value
- * of the spinlock variable is returned, either SP_LOCKED if the spinlock
- * as previously locked (meaning that the test-and-set operation failed to
- * obtain the lock) or SP_UNLOCKED if the spinlock was previously unlocked
- * (meaning that we successfully obtained the lock)
- *
- ****************************************************************************/
-
-/* See prototype in nuttx/include/nuttx/spinlock.h */
-
-#endif /* __ARCH_SIM_INCLUDE_SPINLOCK_H */
diff --git a/arch/sim/src/Makefile b/arch/sim/src/Makefile
index 932ec51dae2..fbd900d8e82 100644
--- a/arch/sim/src/Makefile
+++ b/arch/sim/src/Makefile
@@ -167,10 +167,6 @@ ifeq ($(CONFIG_STACK_COLORATION),y)
CSRCS += sim_checkstack.c
endif
-ifeq ($(CONFIG_SPINLOCK),y)
- HOSTSRCS += sim_testset.c
-endif
-
ifeq ($(CONFIG_SMP),y)
CSRCS += sim_smpsignal.c sim_cpuidlestack.c
endif
diff --git a/arch/sim/src/sim/CMakeLists.txt b/arch/sim/src/sim/CMakeLists.txt
index 529c978269a..43a1427d946 100644
--- a/arch/sim/src/sim/CMakeLists.txt
+++ b/arch/sim/src/sim/CMakeLists.txt
@@ -183,10 +183,6 @@ if(CONFIG_SIM_VIDEO_ENCODER)
list(APPEND SRCS sim_x264encoder.c)
endif()
-if(CONFIG_SPINLOCK)
- list(APPEND HOSTSRCS sim_testset.c)
-endif()
-
if(CONFIG_SMP)
list(APPEND SRCS sim_smpsignal.c sim_cpuidlestack.c)
endif()
diff --git a/arch/sim/src/sim/posix/sim_testset.c
b/arch/sim/src/sim/posix/sim_testset.c
deleted file mode 100644
index 08ac32b57e6..00000000000
--- a/arch/sim/src/sim/posix/sim_testset.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/****************************************************************************
- * arch/sim/src/sim/posix/sim_testset.c
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements. See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership. The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <stdint.h>
-#include <stdatomic.h>
-
-#include "sim_internal.h"
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: up_testset
- *
- * Description:
- * Perform an atomic test and set operation on the provided spinlock.
- *
- * This function must be provided via the architecture-specific logic.
- *
- * Input Parameters:
- * lock - A reference to the spinlock object.
- *
- * Returned Value:
- * The spinlock is always locked upon return. The previous value of the
- * spinlock variable is returned, either SP_LOCKED if the spinlock was
- * previously locked (meaning that the test-and-set operation failed to
- * obtain the lock) or SP_UNLOCKED if the spinlock was previously unlocked
- * (meaning that we successfully obtained the lock).
- *
- ****************************************************************************/
-
-uint8_t up_testset(volatile uint8_t *lock)
-{
-#ifdef CONFIG_SMP
- /* In the multi-CPU SMP case, we use atomic operation to assure that the
- * following test and set is atomic.
- */
-
- return atomic_exchange((_Atomic uint8_t *)lock, 1);
-#else
-
- /* In the non-SMP case, the simulation is implemented with a single thread
- * the test-and-set operation is inherently atomic.
- */
-
- uint8_t ret = *lock;
- *lock = 1;
- return ret;
-#endif
-}
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index 4f950eee3b2..547e6e60c28 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -42,7 +42,6 @@ config ARCH_CHIP_S698PM
select ARCH_VECNOTIRQ
select ARCH_HAVE_RAMFUNCS
select ARCH_HAVE_MULTICPU
- select ARCH_HAVE_TESTSET
select ARCH_HAVE_SERIAL_TERMIOS
---help---
ORBITA Sailing S698PM (ARCH_SPARC_V8)
diff --git a/arch/sparc/include/spinlock.h b/arch/sparc/include/spinlock.h
deleted file mode 100644
index 6ae6ca84394..00000000000
--- a/arch/sparc/include/spinlock.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/****************************************************************************
- * arch/sparc/include/spinlock.h
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements. See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership. The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-#ifndef __ARCH_SPARC_INCLUDE_SPINLOCK_H
-#define __ARCH_SPARC_INCLUDE_SPINLOCK_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-# include <stdint.h>
-#endif /* __ASSEMBLY__ */
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-#define SP_UNLOCKED 0 /* The Un-locked state */
-#define SP_LOCKED 1 /* The Locked state */
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/* The Type of a spinlock.
- *
- * This must be a uint32_ because it will be set using CASA instruction.
- * That instruction atomically Compare the 32-bitvalues in the register
- * and memory, if its current value is the expected one. swap the values
- * of second register with the memory.
- */
-
-typedef uint32_t spinlock_t;
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * Name: up_testset
- *
- * Description:
- * Perform an atomic test and set operation on the provided spinlock.
- *
- * This function must be provided via the architecture-specific logic.
- *
- * Input Parameters:
- * lock - The address of spinlock object.
- *
- * Returned Value:
- * The spinlock is always locked upon return. The value of previous value
- * of the spinlock variable is returned, either SP_LOCKED if the spinlock
- * as previously locked (meaning that the test-and-set operation failed to
- * obtain the lock) or SP_UNLOCKED if the spinlock was previously unlocked
- * (meaning that we successfully obtained the lock)
- *
- ****************************************************************************/
-
-/* See prototype in nuttx/include/nuttx/spinlock.h */
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_SPARC_INCLUDE_SPINLOCK_H */
diff --git a/arch/sparc/src/common/Make.defs b/arch/sparc/src/common/Make.defs
index a1217ecf3ae..a0c0ea652ba 100644
--- a/arch/sparc/src/common/Make.defs
+++ b/arch/sparc/src/common/Make.defs
@@ -34,7 +34,3 @@ CMN_CSRCS += sparc_usestack.c sparc_tcbinfo.c
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += sparc_checkstack.c
endif
-
-ifeq ($(CONFIG_SPINLOCK),y)
-CMN_CSRCS += sparc_testset.c
-endif
diff --git a/arch/sparc/src/common/sparc_testset.c
b/arch/sparc/src/common/sparc_testset.c
deleted file mode 100644
index e7e2c829b57..00000000000
--- a/arch/sparc/src/common/sparc_testset.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/****************************************************************************
- * arch/sparc/src/common/sparc_testset.c
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements. See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership. The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#include <nuttx/spinlock.h>
-
-#ifdef CONFIG_SPINLOCK
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: sparc_compareset
- *
- * Description:
- * Wrapper for the Sparc compare-and-swap instruction. This function will
- * atomically compare *addr to compare, and if it's the same, will swap
- * *addr with set. It will return the value of set which is the old value
- * of *addr.
- *
- * Note: The ldstub and swap instructions are available in all LEON
- * processors, while casa is optional. The CASA is a SPARC-V9 Compare and
- * Swap Alternative instruction but LEON3(GR712R) and LEON4 implements the
- * SPARC V9 Compare and Swap Alternative (CASA) instruction. The CASA
- * operates as described in the SPARC-V9 manual. This instruction is
- * privileged, except when setting ASI = 0xA (user data). All multi-core
- * LEON based components from Cobham Gaisler have casa. According to BCC
- * User's Manual the GCC option -mcpu=leon3 is required to generate SPARC-V8
- * code but support for the casa instruction.
- *
- ****************************************************************************/
-
-static inline uint32_t sparc_compareset(volatile uint32_t *addr,
- uint32_t compare,
- uint32_t set)
-{
- __asm__ __volatile__
- (
- "casa [%2] 0xb, %3, %0\n" /* Atomically compare [%2] to %3, and swap
- * [%2] with %0 if the lock is the same as
- * compare, otherwise, no write-access.
- */
- : "=&r" (set) : "0" (set), "r" (addr), "r" (compare) : "memory"
- );
-
- return set;
-}
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: up_testset
- *
- * Description:
- * Perform an atomic compare and swap operation on the provided spinlock.
- *
- * This function must be provided via the architecture-specific logic.
- *
- * Input Parameters:
- * lock - A reference to the spinlock object.
- *
- * Returned Value:
- * The spinlock is always locked upon return. The previous value of the
- * spinlock variable is returned, either SP_LOCKED if the spinlock was
- * previously locked (meaning that the test-and-set operation failed to
- * obtain the lock) or SP_UNLOCKED if the spinlock was previously unlocked
- * (meaning that we successfully obtained the lock).
- *
- ****************************************************************************/
-
-spinlock_t up_testset(volatile spinlock_t *lock)
-{
- /* Perform the 32-bit compare and set operation */
-
- return sparc_compareset((volatile uint32_t *)lock,
- SP_UNLOCKED, SP_LOCKED);
-}
-
-#endif /* CONFIG_SPINLOCK */
diff --git a/arch/tricore/Kconfig b/arch/tricore/Kconfig
index 0101a683603..ae842be36c0 100644
--- a/arch/tricore/Kconfig
+++ b/arch/tricore/Kconfig
@@ -32,7 +32,6 @@ config ARCH_TC1V6
select ARCH_HAVE_PERF_EVENTS_USER_ACCESS
select ARCH_HAVE_SETJMP
select ARCH_HAVE_RESET
- select ARCH_HAVE_TESTSET
select ARCH_SETJMP_H
default n
@@ -48,7 +47,6 @@ config ARCH_TC1V8
select ARCH_HAVE_POWEROFF
select ARCH_HAVE_SETJMP
select ARCH_HAVE_RESET
- select ARCH_HAVE_TESTSET
select ARCH_SETJMP_H
default n
diff --git a/arch/tricore/include/arch.h b/arch/tricore/include/arch.h
index 811d843e7bc..771cf9bb2c1 100644
--- a/arch/tricore/include/arch.h
+++ b/arch/tricore/include/arch.h
@@ -38,6 +38,8 @@
# include <stddef.h>
#endif
+#include <arch/barriers.h>
+
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
diff --git a/arch/tricore/include/spinlock.h b/arch/tricore/include/spinlock.h
deleted file mode 100644
index b86d178bd00..00000000000
--- a/arch/tricore/include/spinlock.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/****************************************************************************
- * arch/tricore/include/spinlock.h
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements. See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership. The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-#ifndef __ARCH_TRICORE_INCLUDE_SPINLOCK_H
-#define __ARCH_TRICORE_INCLUDE_SPINLOCK_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-# include <stdint.h>
-#endif /* __ASSEMBLY__ */
-
-#include <arch/barriers.h>
-
-/****************************************************************************
- * Pre-processor Prototypes
- ****************************************************************************/
-
-/* Spinlock states */
-
-#define SP_UNLOCKED 0 /* The Un-locked state */
-#define SP_LOCKED 1 /* The Locked state */
-
-/* Memory barriers for use with NuttX spinlock logic
- *
- * Data Memory Barrier (DMB) acts as a memory barrier.
- * Data Synchronization Barrier (DSB) acts as a special kind of memory
- * barrier.
- */
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/* The Type of a spinlock. */
-
-typedef long spinlock_t;
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * Name: up_testset
- *
- * Description:
- * Perform an atomic test and set operation on the provided spinlock.
- *
- * This function must be provided via the architecture-specific logic.
- *
- * Input Parameters:
- * lock - The address of spinlock object.
- *
- * Returned Value:
- * The spinlock is always locked upon return. The value of previous value
- * of the spinlock variable is returned, either SP_LOCKED if the spinlock
- * as previously locked (meaning that the test-and-set operation failed to
- * obtain the lock) or SP_UNLOCKED if the spinlock was previously unlocked
- * (meaning that we successfully obtained the lock)
- *
- ****************************************************************************/
-
-/* See prototype in nuttx/include/nuttx/spinlock.h */
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_TRICORE_INCLUDE_SPINLOCK_H */
diff --git a/arch/tricore/src/common/CMakeLists.txt
b/arch/tricore/src/common/CMakeLists.txt
index 91767ed2bbd..c82566891d5 100644
--- a/arch/tricore/src/common/CMakeLists.txt
+++ b/arch/tricore/src/common/CMakeLists.txt
@@ -53,10 +53,6 @@ if(CONFIG_ENABLE_ALL_SIGNALS)
list(APPEND SRCS tricore_schedulesigaction.c tricore_sigdeliver.c)
endif()
-if(CONFIG_SPINLOCK)
- list(APPEND SRCS tricore_testset.c)
-endif()
-
if(CONFIG_ARCH_USE_MPU)
list(APPEND SRCS tricore_mpu.c)
endif()
diff --git a/arch/tricore/src/common/Make.defs
b/arch/tricore/src/common/Make.defs
index a73d35c5765..8431442beba 100644
--- a/arch/tricore/src/common/Make.defs
+++ b/arch/tricore/src/common/Make.defs
@@ -54,10 +54,6 @@ ifeq ($(CONFIG_ENABLE_ALL_SIGNALS),y)
CMN_CSRCS += tricore_schedulesigaction.c tricore_sigdeliver.c
endif
-ifeq ($(CONFIG_SPINLOCK),y)
- CMN_CSRCS += tricore_testset.c
-endif
-
ifeq ($(CONFIG_ARCH_USE_MPU),y)
CMN_CSRCS += tricore_mpu.c
endif
diff --git a/arch/tricore/src/common/tricore_testset.c
b/arch/tricore/src/common/tricore_testset.c
deleted file mode 100644
index e660ad72d80..00000000000
--- a/arch/tricore/src/common/tricore_testset.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/****************************************************************************
- * arch/tricore/src/common/tricore_testset.c
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements. See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership. The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#include <nuttx/arch.h>
-#include <nuttx/spinlock.h>
-
-#include "tricore_internal.h"
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: up_testset
- *
- * Description:
- * Perform an atomic test and set operation on the provided spinlock.
- * This function must be provided via the architecture-specific logic.
- *
- * Input Parameters:
- * lock - A reference to the spinlock object.
- *
- * Returned Value:
- * The spinlock is always locked upon return. The previous value of the
- * spinlock variable is returned, either SP_LOCKED if the spinlock was
- * previously locked (meaning that the test-and-set operation failed to
- * obtain the lock) or SP_UNLOCKED if the spinlock was previously unlocked
- * (meaning that we successfully obtained the lock).
- *
- ****************************************************************************/
-
-spinlock_t up_testset(volatile spinlock_t *lock)
-{
- /* Perform the compare and set operation */
-
- return Ifx__cmpAndSwap((volatile void *)lock, SP_LOCKED, SP_UNLOCKED);
-}
-
diff --git a/arch/x86_64/include/arch.h b/arch/x86_64/include/arch.h
index 45ad2229601..10baa5ae67c 100644
--- a/arch/x86_64/include/arch.h
+++ b/arch/x86_64/include/arch.h
@@ -35,9 +35,11 @@
#include <sys/types.h>
+#include <arch/barriers.h>
+
/* Include chip-specific definitions */
-# include <arch/chip/arch.h>
+#include <arch/chip/arch.h>
/* Include architecture-specific definitions */
diff --git a/arch/x86_64/include/spinlock.h b/arch/x86_64/include/spinlock.h
deleted file mode 100644
index e7705e820d3..00000000000
--- a/arch/x86_64/include/spinlock.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/****************************************************************************
- * arch/x86_64/include/spinlock.h
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements. See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership. The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-#ifndef __ARCH_X86_64_INCLUDE_SPINLOCK_H
-#define __ARCH_X86_64_INCLUDE_SPINLOCK_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-# include <stdint.h>
-#endif /* __ASSEMBLY__ */
-
-#include <arch/barriers.h>
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* Spinlock states */
-
-#define SP_UNLOCKED 0 /* The Un-locked state */
-#define SP_LOCKED 1 /* The Locked state */
-
-/* Memory barriers for use with NuttX spinlock logic
- *
- * Data Memory Barrier (DMB) acts as a memory barrier. It ensures that all
- * explicit memory accesses that appear in program order before the DMB
- * instruction are observed before any explicit memory accesses that appear
- * in program order after the DMB instruction. It does not affect the
- * ordering of any other instructions executing on the processor
- *
- * Data Synchronization Barrier (DSB) acts as a special kind of memory
- * barrier. No instruction in program order after this instruction executes
- * until this instruction completes. This instruction completes when: (1) All
- * explicit memory accesses before this instruction complete, and (2) all
- * Cache, Branch predictor and TLB maintenance operations before this
- * instruction complete.
- *
- */
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/* The Type of a spinlock */
-
-typedef uintptr_t spinlock_t;
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * Name: up_testset
- *
- * Description:
- * Perform an atomic test and set operation on the provided spinlock.
- *
- * This function must be provided via the architecture-specific logic.
- *
- * Input Parameters:
- * lock - The address of spinlock object.
- *
- * Returned Value:
- * The spinlock is always locked upon return. The value of previous value
- * of the spinlock variable is returned, either SP_LOCKED if the spinlock
- * as previously locked (meaning that the test-and-set operation failed to
- * obtain the lock) or SP_UNLOCKED if the spinlock was previously unlocked
- * (meaning that we successfully obtained the lock)
- *
- ****************************************************************************/
-
-/* See prototype in nuttx/include/nuttx/spinlock.h */
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_X86_64_INCLUDE_SPINLOCK_H */
diff --git a/arch/x86_64/src/intel64/CMakeLists.txt
b/arch/x86_64/src/intel64/CMakeLists.txt
index 41d39f2f218..b25dda06cde 100644
--- a/arch/x86_64/src/intel64/CMakeLists.txt
+++ b/arch/x86_64/src/intel64/CMakeLists.txt
@@ -71,10 +71,6 @@ if(CONFIG_MM_PGALLOC)
list(APPEND SRCS intel64_pgalloc.c)
endif()
-if(CONFIG_ARCH_HAVE_TESTSET)
- list(APPEND SRCS intel64_testset.S)
-endif()
-
if(CONFIG_SMP)
list(APPEND SRCS intel64_cpuidlestack.c intel64_smpcall.c intel64_cpustart.c)
endif()
diff --git a/arch/x86_64/src/intel64/Make.defs
b/arch/x86_64/src/intel64/Make.defs
index 2c98efe6f51..e7c536e7772 100644
--- a/arch/x86_64/src/intel64/Make.defs
+++ b/arch/x86_64/src/intel64/Make.defs
@@ -59,10 +59,6 @@ ifeq ($(CONFIG_MM_PGALLOC),y)
CHIP_CSRCS += intel64_pgalloc.c
endif
-ifeq ($(CONFIG_ARCH_HAVE_TESTSET),y)
-CHIP_ASRCS += intel64_testset.S
-endif
-
ifeq ($(CONFIG_SMP),y)
CHIP_CSRCS += intel64_cpuidlestack.c
CHIP_CSRCS += intel64_smpcall.c
diff --git a/arch/x86_64/src/intel64/intel64_testset.S
b/arch/x86_64/src/intel64/intel64_testset.S
deleted file mode 100644
index 2b306743772..00000000000
--- a/arch/x86_64/src/intel64/intel64_testset.S
+++ /dev/null
@@ -1,73 +0,0 @@
-/****************************************************************************
- * arch/x86/src/intel64/intel64_testset.S
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements. See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership. The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-#include <arch/spinlock.h>
-
- .file "intel64_head.S"
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/**************************************************************************
- * .text
- **************************************************************************/
-
- .text
- .code64
-
-/****************************************************************************
- * Name: up_testset
- *
- * Description:
- * Perform an atomic test and set operation on the provided spinlock.
- *
- * This function must be provided via the architecture-specific logic.
- *
- * Input Parameters:
- * lock - A reference to the spinlock object.
- *
- * Returned Value:
- * The spinlock is always locked upon return. The previous value of the
- * spinlock variable is returned, either SP_LOCKED if the spinlock was
- * previously locked (meaning that the test-and-set operation failed to
- * obtain the lock) or SP_UNLOCKED if the spinlock was previously unlocked
- * (meaning that we successfully obtained the lock).
- *
- ****************************************************************************/
-
- .globl up_testset
- .type up_testset, @function
-up_testset:
- /* Set the value to be written (SP_LOCKED for test-and-set) */
-
- movq $SP_LOCKED, %rax
-
- /* Atomic exchange, the old value is returned in rax */
-
- xchg %rax, (%rdi)
- ret
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index b4ec0f3eedb..dd7c453c703 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -19,7 +19,6 @@ config ARCH_CHIP_ESP32
select ARCH_HAVE_MPU
select ARCH_HAVE_MULTICPU
select ARCH_HAVE_RESET
- select ARCH_HAVE_TESTSET
select ARCH_HAVE_TEXT_HEAP
select ARCH_VECNOTIRQ
select ARCH_MINIMAL_VECTORTABLE
@@ -91,7 +90,6 @@ config ARCH_CHIP_ESP32S3
select ARCH_HAVE_TEXT_HEAP
select ARCH_HAVE_TEXT_HEAP_SEPARATE_DATA_ADDRESS
select ARCH_HAVE_TEXT_HEAP_WORD_ALIGNED_READ
- select ARCH_HAVE_TESTSET
select ARCH_DCACHE
select ARCH_ICACHE
select ARCH_VECNOTIRQ
diff --git a/arch/xtensa/include/spinlock.h b/arch/xtensa/include/spinlock.h
deleted file mode 100644
index 700fe382162..00000000000
--- a/arch/xtensa/include/spinlock.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/****************************************************************************
- * arch/xtensa/include/spinlock.h
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements. See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership. The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-#ifndef __ARCH_XTENSA_INCLUDE_SPINLOCK_H
-#define __ARCH_XTENSA_INCLUDE_SPINLOCK_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-# include <stdint.h>
-#endif /* __ASSEMBLY__ */
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-#define SP_UNLOCKED 0 /* The Un-locked state */
-#define SP_LOCKED 1 /* The Locked state */
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/* The Type of a spinlock.
- *
- * This must be a uint32_ because it will be set using S32C1I instruction.
- * That instruction atomically stores to a memory location only if its
- * current value is the expected one. The state register (SCOMPARE1) is
- * used to provide the additional comparison operand. Some implementations
- * also have a state register (ATOMCTL) for further control of the atomic
- * operation in cache and on the PIF bus.
- */
-
-typedef uint32_t spinlock_t;
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * Name: up_testset
- *
- * Description:
- * Perform an atomic test and set operation on the provided spinlock.
- *
- * This function must be provided via the architecture-specific logic.
- *
- * Input Parameters:
- * lock - The address of spinlock object.
- *
- * Returned Value:
- * The spinlock is always locked upon return. The value of previous value
- * of the spinlock variable is returned, either SP_LOCKED if the spinlock
- * as previously locked (meaning that the test-and-set operation failed to
- * obtain the lock) or SP_UNLOCKED if the spinlock was previously unlocked
- * (meaning that we successfully obtained the lock)
- *
- ****************************************************************************/
-
-#if defined(CONFIG_SPINLOCK)
-static inline_function spinlock_t up_testset(volatile spinlock_t *lock)
-{
- /* Perform the 32-bit compare and set operation */
-
- spinlock_t ret;
-
- __asm__ __volatile__
- (
- "WSR %2, SCOMPARE1\n" /* Initialize SCOMPARE1 */
- "S32C1I %0, %1, 0\n" /* Store the compare value into the lock,
- * if the lock is the same as compare1.
- * Otherwise, no write-access */
- : "=r"(ret) : "r"(lock), "r"(SP_UNLOCKED), "0"(SP_LOCKED)
- );
-
- return ret;
-}
-#endif
-
-/* See prototype in nuttx/include/nuttx/spinlock.h */
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_XTENSA_INCLUDE_SPINLOCK_H */
diff --git a/include/nuttx/arch.h b/include/nuttx/arch.h
index 91492fefe9c..2836a57cd46 100644
--- a/include/nuttx/arch.h
+++ b/include/nuttx/arch.h
@@ -2286,78 +2286,6 @@ void up_tls_initialize(FAR struct tls_info_s *info);
#define up_tls_initialize(x)
#endif
-/****************************************************************************
- * Multiple CPU support
- ****************************************************************************/
-
-/****************************************************************************
- * Name: up_testset
- *
- * Description:
- * Perform an atomic test and set operation on the provided spinlock.
- *
- * Input Parameters:
- * lock - The address of spinlock object.
- *
- * Returned Value:
- * The spinlock is always locked upon return. The value of previous value
- * of the spinlock variable is returned, either SP_LOCKED if the spinlock
- * was previously locked (meaning that the test-and-set operation failed to
- * obtain the lock) or SP_UNLOCKED if the spinlock was previously unlocked
- * (meaning that we successfully obtained the lock)
- *
- ****************************************************************************/
-
-/* See prototype in include/nuttx/spinlock.h */
-
-/****************************************************************************
- * Name: up_fetchadd8, up_fetchadd16, and up_fetchadd32
- *
- * Description:
- * Perform an atomic fetch add operation on the provided 8-, 16-, or 32-
- * bit value.
- *
- * This function must be provided via the architecture-specific logic.
- *
- * Input Parameters:
- * addr - The address of value to be incremented.
- * value - The addend
- *
- * Returned Value:
- * The incremented value (volatile!)
- *
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_HAVE_FETCHADD
-int32_t up_fetchadd32(FAR volatile int32_t *addr, int32_t value);
-int16_t up_fetchadd16(FAR volatile int16_t *addr, int16_t value);
-int8_t up_fetchadd8(FAR volatile int8_t *addr, int8_t value);
-#endif
-
-/****************************************************************************
- * Name: up_fetchsub8
- *
- * Description:
- * Perform an atomic fetch subtract operation on the provided 8-, 16-, or
- * 32-bit value.
- *
- * This function must be provided via the architecture-specific logic.
- *
- * Input Parameters:
- * addr - The address of value to be decremented.
- * value - The subtrahend
- *
- * Returned Value:
- * The decremented value (volatile!)
- *
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_HAVE_FETCHADD
-int32_t up_fetchsub32(FAR volatile int32_t *addr, int32_t value);
-int16_t up_fetchsub16(FAR volatile int16_t *addr, int16_t value);
-int8_t up_fetchsub8(FAR volatile int8_t *addr, int8_t value);
-#endif
-
/****************************************************************************
* Name: up_cpu_idlestack
*
diff --git a/include/nuttx/spinlock.h b/include/nuttx/spinlock.h
index 3832bad3960..bcf65540506 100644
--- a/include/nuttx/spinlock.h
+++ b/include/nuttx/spinlock.h
@@ -76,49 +76,6 @@ void nxsched_critmon_busywait(bool state, FAR void *caller);
* Public Data Types
****************************************************************************/
-/****************************************************************************
- * Name: up_testset
- *
- * Description:
- * Perform an atomic test and set operation on the provided spinlock.
- *
- * This function must be provided via the architecture-specific logic.
- *
- * Input Parameters:
- * lock - A reference to the spinlock object.
- *
- * Returned Value:
- * The spinlock is always locked upon return. The previous value of the
- * spinlock variable is returned, either SP_LOCKED if the spinlock was
- * previously locked (meaning that the test-and-set operation failed to
- * obtain the lock) or SP_UNLOCKED if the spinlock was previously unlocked
- * (meaning that we successfully obtained the lock).
- *
- ****************************************************************************/
-
-#if defined(CONFIG_ARCH_HAVE_TESTSET)
-spinlock_t up_testset(FAR volatile spinlock_t *lock);
-#else
-static inline spinlock_t up_testset(FAR volatile spinlock_t *lock)
-{
- irqstate_t flags;
- spinlock_t ret;
-
- flags = up_irq_save();
-
- ret = *lock;
-
- if (ret == SP_UNLOCKED)
- {
- *lock = SP_LOCKED;
- }
-
- up_irq_restore(flags);
-
- return ret;
-}
-#endif
-
/****************************************************************************
* Name: spin_lock_init
*
@@ -183,17 +140,11 @@ static inline_function void rspin_lock_init(FAR
rspinlock_t *lock)
static inline_function void spin_lock_notrace(FAR volatile spinlock_t *lock)
{
#ifdef CONFIG_TICKET_SPINLOCK
- int ticket = atomic_add(&lock->next, 1);
- while (atomic_read(&lock->owner) != ticket)
+ int ticket = atomic_add_relaxed(&lock->next, 1);
+ while (atomic_read_acquire(&lock->owner) != ticket);
#else /* CONFIG_TICKET_SPINLOCK */
- while (up_testset(lock) == SP_LOCKED)
+ while (atomic_xchg_acquire((FAR atomic_t *)lock, SP_LOCKED) == SP_LOCKED);
#endif
- {
- UP_DSB();
- UP_WFE();
- }
-
- UP_DMB();
}
#else
# define spin_lock_notrace(lock)
@@ -287,17 +238,10 @@ spin_trylock_notrace(FAR volatile spinlock_t *lock)
uint32_t expected = atomic_read(&lock->owner);
- if (!atomic_cmpxchg(&lock->next, &expected, expected + 1))
+ return atomic_cmpxchg_acquire(&lock->next, &expected, expected + 1);
#else /* CONFIG_TICKET_SPINLOCK */
- if (up_testset(lock) == SP_LOCKED)
+ return atomic_xchg_acquire((FAR atomic_t *)lock, SP_LOCKED) != SP_LOCKED;
#endif /* CONFIG_TICKET_SPINLOCK */
- {
- UP_DSB();
- return false;
- }
-
- UP_DMB();
- return true;
}
#endif /* CONFIG_SPINLOCK */
@@ -373,14 +317,11 @@ static inline_function bool spin_trylock(FAR volatile
spinlock_t *lock)
static inline_function void
spin_unlock_notrace(FAR volatile spinlock_t *lock)
{
- UP_DMB();
#ifdef CONFIG_TICKET_SPINLOCK
- atomic_add(&lock->owner, 1);
+ atomic_add_release(&lock->owner, 1);
#else
- *lock = SP_UNLOCKED;
+ atomic_set_release((FAR atomic_t *)lock, SP_UNLOCKED);
#endif
- UP_DSB();
- UP_SEV();
}
#else
# define spin_unlock_notrace(lock)
@@ -1021,20 +962,14 @@ static inline_function void read_lock(FAR volatile
rwlock_t *lock)
while (true)
{
int old = atomic_read(lock);
- if (old <= RW_SP_WRITE_LOCKED)
- {
- DEBUGASSERT(old == RW_SP_WRITE_LOCKED);
- UP_DSB();
- UP_WFE();
- }
- else if(atomic_cmpxchg(lock, &old, old + 1))
+
+ if (old > RW_SP_WRITE_LOCKED &&
+ atomic_cmpxchg_acquire(lock, &old, old + 1))
{
break;
}
}
- UP_DMB();
-
nxsched_critmon_busywait(false, return_address(0));
}
@@ -1068,12 +1003,13 @@ static inline_function bool read_trylock(FAR volatile
rwlock_t *lock)
while (true)
{
int old = atomic_read(lock);
+
if (old <= RW_SP_WRITE_LOCKED)
{
DEBUGASSERT(old == RW_SP_WRITE_LOCKED);
return false;
}
- else if (atomic_cmpxchg(lock, &old, old + 1))
+ else if (atomic_cmpxchg_acquire(lock, &old, old + 1))
{
break;
}
@@ -1104,10 +1040,7 @@ static inline_function void read_unlock(FAR volatile
rwlock_t *lock)
{
DEBUGASSERT(atomic_read(lock) >= RW_SP_READ_LOCKED);
- UP_DMB();
- atomic_sub(lock, 1);
- UP_DSB();
- UP_SEV();
+ atomic_sub_release(lock, 1);
}
/****************************************************************************
@@ -1143,17 +1076,13 @@ static inline_function void write_lock(FAR volatile
rwlock_t *lock)
while (true)
{
int zero = RW_SP_UNLOCKED;
- if (atomic_cmpxchg((FAR atomic_int *)lock, &zero, RW_SP_WRITE_LOCKED))
+ if (atomic_cmpxchg_acquire((FAR atomic_int *)lock, &zero,
+ RW_SP_WRITE_LOCKED))
{
break;
}
-
- UP_DSB();
- UP_WFE();
}
- UP_DMB();
-
nxsched_critmon_busywait(false, return_address(0));
}
@@ -1187,14 +1116,7 @@ static inline_function bool write_trylock(FAR volatile
rwlock_t *lock)
{
int zero = RW_SP_UNLOCKED;
- if (atomic_cmpxchg(lock, &zero, RW_SP_WRITE_LOCKED))
- {
- UP_DMB();
- return true;
- }
-
- UP_DSB();
- return false;
+ return atomic_cmpxchg_acquire(lock, &zero, RW_SP_WRITE_LOCKED);
}
/****************************************************************************
@@ -1220,10 +1142,7 @@ static inline_function void write_unlock(FAR volatile
rwlock_t *lock)
DEBUGASSERT(atomic_read(lock) == RW_SP_WRITE_LOCKED);
- UP_DMB();
- atomic_set(lock, RW_SP_UNLOCKED);
- UP_DSB();
- UP_SEV();
+ atomic_set_release(lock, RW_SP_UNLOCKED);
}
/****************************************************************************
diff --git a/include/nuttx/spinlock_type.h b/include/nuttx/spinlock_type.h
index 5781c588874..fa106c17e41 100644
--- a/include/nuttx/spinlock_type.h
+++ b/include/nuttx/spinlock_type.h
@@ -67,17 +67,10 @@ typedef struct spinlock_s
#else
-/* The architecture specific spinlock.h header file must also provide the
- * following:
- *
- * SP_LOCKED - A definition of the locked state value (usually 1)
- * SP_UNLOCKED - A definition of the unlocked state value (usually 0)
- * spinlock_t - The type of a spinlock memory object.
- *
- * SP_LOCKED and SP_UNLOCKED must be constants of type spinlock_t.
- */
+typedef uint32_t spinlock_t;
-#include <arch/spinlock.h>
+# define SP_UNLOCKED 0
+# define SP_LOCKED 1
#endif /* CONFIG_SPINLOCK */
diff --git a/sched/Kconfig b/sched/Kconfig
index bac8e961aa2..ed0e8c512f4 100644
--- a/sched/Kconfig
+++ b/sched/Kconfig
@@ -344,7 +344,6 @@ config SMP
bool "Symmetric Multi-Processing (SMP)"
default n
depends on ARCH_HAVE_MULTICPU
- depends on ARCH_HAVE_TESTSET
depends on ARCH_INTERRUPTSTACK != 0
select SPINLOCK
select IRQCOUNT
