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commit 72e468de8ff13672ca808275537c186aebd4a881 Author: Darryl Ring <[email protected]> AuthorDate: Fri Sep 11 16:21:31 2026 -0700 boards/arm/stm32h5/nucleo-h563zi: Configure MPU If CONFIG_ARM_MPU and CONFIG_STM32_ICACHE are set, this will configure an MPU region marking the OTP flash as non-cacheable. This prevents hard faults when accessing the 4K OTP region from software. Signed-off-by: Darryl Ring <[email protected]> --- .../src/stm32h5/hardware/stm32h5xxx_memorymap.h | 1 + .../arm/stm32h5/nucleo-h563zi/src/CMakeLists.txt | 4 +++ boards/arm/stm32h5/nucleo-h563zi/src/Make.defs | 4 +++ .../arm/stm32h5/nucleo-h563zi/src/nucleo-h563zi.h | 12 +++++++ boards/arm/stm32h5/nucleo-h563zi/src/stm32_boot.c | 6 ++++ boards/arm/stm32h5/nucleo-h563zi/src/stm32_mpu.c | 41 ++++++++++++++++++++++ 6 files changed, 68 insertions(+) diff --git a/arch/arm/src/stm32h5/hardware/stm32h5xxx_memorymap.h b/arch/arm/src/stm32h5/hardware/stm32h5xxx_memorymap.h index ea0bc9e05ff..d36327ea3d2 100644 --- a/arch/arm/src/stm32h5/hardware/stm32h5xxx_memorymap.h +++ b/arch/arm/src/stm32h5/hardware/stm32h5xxx_memorymap.h @@ -60,6 +60,7 @@ /* System Memory Addresses **************************************************/ #define STM32_SYSMEM_MEM 0x0bf80000 +#define STM32_OTP_BASE 0x08FFF000 /* One-Time Programmable (OTP) memory base address */ #define STM32_SYSMEM_UID 0x08FFF800 /* The 96-bit unique device identifier */ #define STM32_SYSMEM_FSIZE 0x08FFF80C /* Size of Flash memory in Kbytes. */ #define STM32_SYSMEM_PACKAGE 0x08FFF80E /* Indicates the device's package type. */ diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/CMakeLists.txt b/boards/arm/stm32h5/nucleo-h563zi/src/CMakeLists.txt index 75c0d6d997b..e6816c82f32 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/src/CMakeLists.txt +++ b/boards/arm/stm32h5/nucleo-h563zi/src/CMakeLists.txt @@ -52,6 +52,10 @@ if(CONFIG_STM32_USBFS_HOST) list(APPEND SRCS stm32_usb.c) endif() +if(CONFIG_ARM_MPU) + list(APPEND SRCS stm32_mpu.c) +endif() + target_sources(board PRIVATE ${SRCS}) set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/Make.defs b/boards/arm/stm32h5/nucleo-h563zi/src/Make.defs index 828ce6c96c1..e51b1e73344 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/src/Make.defs +++ b/boards/arm/stm32h5/nucleo-h563zi/src/Make.defs @@ -58,6 +58,10 @@ ifeq ($(CONFIG_STM32_USBFS_HOST),y) CSRCS += stm32_usb.c endif +ifeq ($(CONFIG_ARM_MPU),y) +CSRCS += stm32_mpu.c +endif + DEPPATH += --dep-path board VPATH += :board CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/nucleo-h563zi.h b/boards/arm/stm32h5/nucleo-h563zi/src/nucleo-h563zi.h index 7bbc2507f82..a19be1144ae 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/src/nucleo-h563zi.h +++ b/boards/arm/stm32h5/nucleo-h563zi/src/nucleo-h563zi.h @@ -115,6 +115,18 @@ int stm32_bringup(void); +/**************************************************************************** + * Name: stm32_mpu_configure_otp + * + * Description: + * Initialize MPU and configure the OTP flash region. + * + ****************************************************************************/ + +#if defined(CONFIG_ARM_MPU) && defined(CONFIG_STM32_ICACHE) +void stm32_mpu_configure_otp(void); +#endif + #ifdef CONFIG_STM32_SPI /**************************************************************************** * Name: stm32_spiregister diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_boot.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_boot.c index a0674b61329..9d33312fb59 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_boot.c +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_boot.c @@ -53,6 +53,12 @@ void stm32_board_initialize(void) { +#if defined(CONFIG_ARM_MPU) && defined(CONFIG_STM32_ICACHE) + /* Configure OTP MPU region. */ + + stm32_mpu_configure_otp(); +#endif + #ifdef CONFIG_ARCH_LEDS /* Configure on-board LEDs if LED support has been selected. */ diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_mpu.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_mpu.c new file mode 100644 index 00000000000..3ac2d4f0e3e --- /dev/null +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_mpu.c @@ -0,0 +1,41 @@ +/**************************************************************************** + * boards/arm/stm32h5/nucleo-h563zi/src/stm32_mpu.c + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <debug.h> +#include <errno.h> + +#include <nuttx/arch.h> + +#include "hardware/stm32_memorymap.h" +#include "mpu.h" +#include "stm32_mpuinit.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_mpu_configure_otp + * + * Description: + * Configure the OTP flash region as non-cacheable, non-executable, non- + * shareable, and read-only. + * + ****************************************************************************/ + +void stm32_mpu_configure_otp(void) +{ + mpu_configure_region(STM32_OTP_BASE, 4096, + MPU_RBAR_XN | MPU_RBAR_SH_NO | MPU_RBAR_AP_RORO, + MPU_RLAR_NONCACHEABLE); +}
