daniel-p-carvalho opened a new pull request, #20152:
URL: https://github.com/apache/nuttx/pull/20152
## Summary
This PR adds support for ADC differential mode selection (DIFSEL) and fixes
auto-calibration for STM32 ADC IPv2 and IPv2G4 (STM32F3 and STM32G4 families).
1. **Hardware Headers (`stm32_adc_v2.h` and `stm32_adc_v2g4.h`)**:
- Fixed register comments and added `ADC_DIFSEL` shift/masks.
2. **Kconfig (`Kconfig.adc`)**:
- Added `menuconfig STM32_ADC_DIFSEL` under `STM32_HAVE_IP_ADC_M3M4_V2`.
- Added per-ADC configuration options: `CONFIG_STM32_ADCx_DIFSEL` and
`CONFIG_STM32_ADCx_DIFSEL_VALUE` bitmask (bit $n$ = channel $n$).
3. **Driver Architecture (`stm32_adc_m3m4_v1v2.h` /
`stm32_adc_m3m4_v1v2.c`)**:
- Added `difselcfg` to ADC private structure and `difselcfg_set` to
lower-half operations.
- Configured `DIFSEL` in `adc_configure()` prior to enabling the ADC
(`adc_enable(priv, true)`), strictly adhering to the ST Reference Manual
(RM0440 / RM0316).
- Re-enabled and fixed `adc_calibrate()` for `HAVE_IP_ADC_V2`: performs
single-ended calibration (`ADCALDIF=0`) and, if differential channels are
configured, differential calibration (`ADCALDIF=1`).
- Cleaned up pre-existing `nxstyle` issues across the driver.
## Impact
- **New feature**: Allows configuring differential analog channels on
STM32F3 and STM32G4 microcontrollers.
- **User impact**: Differential mode can now be enabled cleanly via
`menuconfig` or board headers.
- **Build impact**: None. Zero impact when `CONFIG_STM32_ADC_DIFSEL` is
disabled.
- **Hardware compatibility**: Fully backwards compatible with existing
single-ended ADC configurations.
## Testing
- **Build Host**: Linux x86_64, arm-none-eabi-gcc 13.3.rel1
- **Target**: STM32G431KB (Nucleo-G431KB), configuration based on
`nucleo-g431rb:adc`
- **Linter**: `./tools/checkpatch.sh -m -g upstream/master..HEAD` passes
with 0 errors and 0 warnings (`✔️ All checks pass.`)
### Hardware Validation Details
Tested on **Nucleo-G431KB** with ADC1 Channel 1 configured as differential
input:
- Non-inverting input ($V_{INP}$): PA0 (Pin A0)
- Inverting input ($V_{INN}$): PA1 (Pin A1)
1. **Zero differential ($V_{INP} = V_{INN} = 0\text{ V}$, both connected to
GND)**:
- Before calibration: reading fluctuated around ~1999 (offset of ~48 LSB).
- After calibration: stabilized cleanly at **`2015`** (expected 12-bit
bipolar midpoint 2048 with minor board noise).
```
Sample:
1: channel: 1 value: 2015
2: channel: 2 value: 20
3: channel: 15 value: 112
```
2. **Positive full scale ($V_{INP} = 3.3\text{ V}$, $V_{INN} = 0\text{
V}$)**:
- Pin A0 connected to 3V3, Pin A1 connected to GND ($V_{diff} =
+3.3\text{ V}$).
- Reading: **`4095`** (maximum positive full-scale).
```
Sample:
1: channel: 1 value: 4095
2: channel: 2 value: 0
3: channel: 15 value: 1863
```
3. **Negative full scale ($V_{INP} = 0\text{ V}$, $V_{INN} = 3.3\text{
V}$)**:
- Pin A0 connected to GND, Pin A1 connected to 3V3 ($V_{diff} =
-3.3\text{ V}$).
- Reading: **`0`** (minimum negative full-scale).
```
Sample:
1: channel: 1 value: 0
2: channel: 2 value: 4095
3: channel: 15 value: 2247
```
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