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xiaoxiang781216 pushed a commit to branch releases/13.1
in repository https://gitbox.apache.org/repos/asf/nuttx.git
The following commit(s) were added to refs/heads/releases/13.1 by this push:
new b755c38d387 arch/arm/stm32h7: poll MDIO completion in microseconds,
not 5 ms steps
b755c38d387 is described below
commit b755c38d38735039be5e0ceb79e0c06a42813b5f
Author: Jacob Dahl <[email protected]>
AuthorDate: Sun Sep 6 19:03:38 2026 -0600
arch/arm/stm32h7: poll MDIO completion in microseconds, not 5 ms steps
stm32_c22_read() and stm32_c22_write() waited for the MACMDIOAR busy bit
with up_mdelay(5) between checks. A Clause 22 frame takes about 30 us,
so the first check always sees the bus busy and every PHY register
access costs a 5 ms busy-wait, roughly 150 times the transfer.
stm32_phyinit() waits for link-up with PHY_RETRY_TIMEOUT (6552) MSR
reads. With no cable attached that is 33 s of CPU spent in
up_mdelay() inside ifup, with the network lock held: on an STM32H753
the netinit thread pinned the core at 44% for the first 65 s after
boot and every socket operation on other threads blocked until it gave
up. Before the MDIO bus refactor, stm32_phyread() polled the busy bit
in a tight loop.
Poll every 10 us instead, with the timeout expressed in microseconds so
the total bound stays at 10 ms, and report the timeout from the result
rather than the loop counter so a transfer that completes on the last
iteration is not logged as timed out.
Signed-off-by: Jacob Dahl <[email protected]>
---
arch/arm/src/stm32h7/stm32_mdio.c | 23 ++++++++++++++---------
1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/arch/arm/src/stm32h7/stm32_mdio.c
b/arch/arm/src/stm32h7/stm32_mdio.c
index 096c0b9d6c8..03d7e13461c 100644
--- a/arch/arm/src/stm32h7/stm32_mdio.c
+++ b/arch/arm/src/stm32h7/stm32_mdio.c
@@ -63,7 +63,7 @@ struct stm32_mdio_lowerhalf_s
{
struct mdio_lowerhalf_s base;
- /* MDIO bus timeout in milliseconds */
+ /* MDIO bus timeout in microseconds */
int timeout;
};
@@ -95,7 +95,7 @@ struct stm32_mdio_lowerhalf_s g_stm32_mdio_lowerhalf =
{
.ops = &g_stm32_mdio_ops
},
- .timeout = 10
+ .timeout = 10000
};
/****************************************************************************
@@ -131,9 +131,14 @@ static int stm32_c22_read(struct mdio_lowerhalf_s *dev,
uint8_t phydev,
stm32_putreg(regval, STM32_ETH_MACMDIOAR);
- /* Wait for the transfer to complete */
+ /* Wait for the transfer to complete. A Clause 22 frame is 64 MDC
+ * cycles, about 30 us at a 2.5 MHz MDC, so poll at a fraction of that.
+ * A millisecond delay here turns every PHY register access into a
+ * busy-wait far longer than the transfer, and the autonegotiation link
+ * wait in stm32_phyinit() issues thousands of them.
+ */
- for (to = priv->timeout; to >= 0; to--)
+ for (to = priv->timeout; to > 0; to -= 10)
{
if ((stm32_getreg(STM32_ETH_MACMDIOAR) & ETH_MACMDIOAR_MB) == 0)
{
@@ -142,10 +147,10 @@ static int stm32_c22_read(struct mdio_lowerhalf_s *dev,
uint8_t phydev,
break;
}
- up_mdelay(5);
+ up_udelay(10);
}
- if (to <= 0)
+ if (retval < 0)
{
ninfo("MII transfer timed out: phydev: %04x regaddr: %04x\n",
phydev, regaddr);
@@ -192,7 +197,7 @@ static int stm32_c22_write(struct mdio_lowerhalf_s *dev,
uint8_t phydev,
/* Wait for the transfer to complete */
- for (to = priv->timeout; to >= 0; to--)
+ for (to = priv->timeout; to > 0; to -= 10)
{
if ((stm32_getreg(STM32_ETH_MACMDIOAR) & ETH_MACMDIOAR_MB) == 0)
{
@@ -200,10 +205,10 @@ static int stm32_c22_write(struct mdio_lowerhalf_s *dev,
uint8_t phydev,
break;
}
- up_mdelay(5);
+ up_udelay(10);
}
- if (to <= 0)
+ if (retval < 0)
{
ninfo("MII transfer timed out: phydevaddr: %04x phyregaddr: %04x"
"value: %04x\n", phydev, regaddr, value);
