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commit 13bfc34db32ca5ec22dcbaff75bfb81711751fba Author: Marcio Ribeiro <[email protected]> AuthorDate: Thu Sep 3 15:25:19 2026 -0300 boards/risc-v/esp32c2/common: add shared board support for ESP32-C2 Add linker scripts and shared board drivers reused by ESP32-C2 boards, and wire common Kconfig into the board configuration tree. Assisted-by: Claude:claude-opus-5 Signed-off-by: Marcio Ribeiro <[email protected]> --- boards/Kconfig | 3 + boards/risc-v/esp32c2/common/.gitignore | 2 + boards/risc-v/esp32c2/common/CMakeLists.txt | 24 + boards/risc-v/esp32c2/common/Kconfig | 58 ++ boards/risc-v/esp32c2/common/Makefile | 35 ++ boards/risc-v/esp32c2/common/scripts/.gitignore | 1 + boards/risc-v/esp32c2/common/scripts/common.ld | 37 ++ .../esp32c2/common/scripts/esp32c2_aliases.ld | 44 ++ .../esp32c2/common/scripts/esp32c2_flat_memory.ld | 106 ++++ .../common/scripts/esp32c2_legacy_sections.ld | 297 ++++++++++ .../esp32c2/common/scripts/esp32c2_sections.ld | 640 +++++++++++++++++++++ boards/risc-v/esp32c2/common/src/CMakeLists.txt | 25 + boards/risc-v/esp32c2/common/src/Make.defs | 29 + 13 files changed, 1301 insertions(+) diff --git a/boards/Kconfig b/boards/Kconfig index 388f19bbd1a..fd3b7353602 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -5569,6 +5569,9 @@ endif if ARCH_CHIP_ESP32C3_LEGACY source "boards/risc-v/esp32c3-legacy/common/Kconfig" endif +if ARCH_CHIP_ESP32C2 +source "boards/risc-v/esp32c2/common/Kconfig" +endif if ARCH_CHIP_ESP32C3 source "boards/risc-v/esp32c3/common/Kconfig" endif diff --git a/boards/risc-v/esp32c2/common/.gitignore b/boards/risc-v/esp32c2/common/.gitignore new file mode 100644 index 00000000000..cc92d189b53 --- /dev/null +++ b/boards/risc-v/esp32c2/common/.gitignore @@ -0,0 +1,2 @@ +etctmp +etctmp.c diff --git a/boards/risc-v/esp32c2/common/CMakeLists.txt b/boards/risc-v/esp32c2/common/CMakeLists.txt new file mode 100644 index 00000000000..f2cf4ae4486 --- /dev/null +++ b/boards/risc-v/esp32c2/common/CMakeLists.txt @@ -0,0 +1,24 @@ +# ############################################################################## +# boards/risc-v/esp32c2/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) +target_include_directories(board PRIVATE include) diff --git a/boards/risc-v/esp32c2/common/Kconfig b/boards/risc-v/esp32c2/common/Kconfig new file mode 100644 index 00000000000..6d2c5f9495e --- /dev/null +++ b/boards/risc-v/esp32c2/common/Kconfig @@ -0,0 +1,58 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +config ESPRESSIF_MERGE_BINS + bool "Merge raw binary files into a single file" + default n + ---help--- + Merge the raw binary files into a single file for flashing to the + device. + This is only useful when the path to binary files (e.g. bootloader) + is provided via the ESPTOOL_BINDIR variable. + +config ESPRESSIF_SPIFLASH_AUTO_BRINGUP + bool "Automatic mount of SPI Flash MTD" + default y + depends on ESPRESSIF_MTD + ---help--- + Auto bring-up the SPI Flash MTD on board bring-up. + If not selected, the MTD will be registered as a device node on /dev. + +choice ESPRESSIF_SPIFLASH_FS + prompt "File system to mount on SPI Flash MTD" + default ESPRESSIF_SPIFLASH_SMARTFS + depends on ESPRESSIF_SPIFLASH_AUTO_BRINGUP + optional + ---help--- + Mount the SPI Flash MTD with the selected File System format on board + bring-up. + If not selected, the MTD will be registered as a device node on /dev. + +config ESPRESSIF_SPIFLASH_SMARTFS + bool "SmartFS" + select FS_SMARTFS + select MTD_SMART + +config ESPRESSIF_SPIFLASH_NXFFS + bool "NXFFS" + select FS_NXFFS + +config ESPRESSIF_SPIFLASH_SPIFFS + bool "SPIFFS" + select FS_SPIFFS + +config ESPRESSIF_SPIFLASH_LITTLEFS + bool "LittleFS" + select FS_LITTLEFS + +config ESPRESSIF_SPIFLASH_MTD_CONFIG + bool "Non-volatile storage" + +endchoice # ESPRESSIF_SPIFLASH_FS + +config ESPRESSIF_SPIFLASH_FS_MOUNT_PT + string "File-system Mount Point" + depends on ESPRESSIF_SPIFLASH_SMARTFS || ESPRESSIF_SPIFLASH_NXFFS || ESPRESSIF_SPIFLASH_SPIFFS || ESPRESSIF_SPIFLASH_LITTLEFS + default "/data" diff --git a/boards/risc-v/esp32c2/common/Makefile b/boards/risc-v/esp32c2/common/Makefile new file mode 100644 index 00000000000..878b58c4d3b --- /dev/null +++ b/boards/risc-v/esp32c2/common/Makefile @@ -0,0 +1,35 @@ +############################################################################# +# boards/risc-v/esp32c3/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +include board/Make.defs +include src/Make.defs + +DEPPATH += --dep-path board +DEPPATH += --dep-path src + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include diff --git a/boards/risc-v/esp32c2/common/scripts/.gitignore b/boards/risc-v/esp32c2/common/scripts/.gitignore new file mode 100644 index 00000000000..0fa3d8108a5 --- /dev/null +++ b/boards/risc-v/esp32c2/common/scripts/.gitignore @@ -0,0 +1 @@ +/*.ld.tmp diff --git a/boards/risc-v/esp32c2/common/scripts/common.ld b/boards/risc-v/esp32c2/common/scripts/common.ld new file mode 100644 index 00000000000..824bc02714b --- /dev/null +++ b/boards/risc-v/esp32c2/common/scripts/common.ld @@ -0,0 +1,37 @@ +/**************************************************************************** + * boards/risc-v/esp32c2/common/scripts/common.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ +#include <nuttx/config.h> + +#if CONFIG_ESPRESSIF_SOC_RTC_MEM_SUPPORTED +# define ESP_BOOTLOADER_RESERVE_RTC 0 + + /* rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files). + * For rtc_timer_data_in_rtc_mem section. + */ +# define RTC_TIMER_RESERVE_RTC (24) + +# ifdef CONFIG_ARCH_CHIP_ESP32 +# define RESERVE_RTC_MEM (RTC_TIMER_RESERVE_RTC) +# else +# define RESERVE_RTC_MEM (ESP_BOOTLOADER_RESERVE_RTC + RTC_TIMER_RESERVE_RTC) +# endif /* CONFIG_ARCH_CHIP_ESP32 */ +#endif /* CONFIG_ESPRESSIF_SOC_RTC_MEM_SUPPORTED */ diff --git a/boards/risc-v/esp32c2/common/scripts/esp32c2_aliases.ld b/boards/risc-v/esp32c2/common/scripts/esp32c2_aliases.ld new file mode 100644 index 00000000000..92629ba7483 --- /dev/null +++ b/boards/risc-v/esp32c2/common/scripts/esp32c2_aliases.ld @@ -0,0 +1,44 @@ +/**************************************************************************** + * boards/risc-v/esp32c2/common/scripts/esp32c2_aliases.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +cache_set_idrom_mmu_size = Cache_Set_IDROM_MMU_Size; +cache_dbus_mmu_set = Cache_Dbus_MMU_Set; +cache_ibus_mmu_set = Cache_Ibus_MMU_Set; +cache_invalidate_icache_all = Cache_Invalidate_ICache_All; +cache_resume_icache = Cache_Resume_ICache; +cache_suspend_icache = Cache_Suspend_ICache; +cache_invalidate_icache_all = Cache_Invalidate_ICache_All; +_interrupt_handler = exception_common; + +#ifdef CONFIG_ESPRESSIF_BLE + +/* Lower-case aliases for BLE library symbols not compliant to nxstyle */ + +api_vhci_host_check_send_available = API_vhci_host_check_send_available; +api_vhci_host_send_packet = API_vhci_host_send_packet; +api_vhci_host_register_callback = API_vhci_host_register_callback; +scan_stack_enable_adv_flow_ctrl_vs_cmd = scan_stack_enableAdvFlowCtrlVsCmd; +adv_stack_enable_clear_legacy_adv_vs_cmd = adv_stack_enableClearLegacyAdvVsCmd; +adv_filter_stack_enable_dup_exc_list_vs_cmd = advFilter_stack_enableDupExcListVsCmd; +chan_sel_stack_enable_set_csa_vs_cmd = chanSel_stack_enableSetCsaVsCmd; + +#endif diff --git a/boards/risc-v/esp32c2/common/scripts/esp32c2_flat_memory.ld b/boards/risc-v/esp32c2/common/scripts/esp32c2_flat_memory.ld new file mode 100644 index 00000000000..5cb5c6d400a --- /dev/null +++ b/boards/risc-v/esp32c2/common/scripts/esp32c2_flat_memory.ld @@ -0,0 +1,106 @@ +/**************************************************************************** + * boards/risc-v/esp32c2/scripts/esp32c2_flat_memory.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * ESP32-C2 Linker Script Memory Layout + * + * This file describes the memory layout (memory blocks) as virtual + * memory addresses. + * + * esp32c2_<legacy/mcuboot>_sections.ld contains output sections to link + * compiler output into these memory blocks. + * + ****************************************************************************/ + +#include "common.ld" +#include "esp32c2_aliases.ld" + +#define SRAM_IRAM_START 0x4037C000 +#define SRAM_DRAM_START 0x3FCA0000 + +/* ICache size is fixed to 16KB on ESP32-C2 */ + +#define ICACHE_SIZE 0x4000 +#define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START + ICACHE_SIZE) + +/* 2nd stage bootloader iram_loader_seg start address */ + +#define SRAM_DRAM_END (0x403AEB70 - I_D_SRAM_OFFSET) + +#define SRAM_IRAM_ORG (SRAM_IRAM_START + ICACHE_SIZE) +#define SRAM_DRAM_ORG (SRAM_DRAM_START) + +#define I_D_SRAM_SIZE (SRAM_DRAM_END - SRAM_DRAM_ORG) + +#ifdef CONFIG_ESPRESSIF_FLASH_2M +# define FLASH_SIZE 0x200000 +#elif defined (CONFIG_ESPRESSIF_FLASH_4M) +# define FLASH_SIZE 0x400000 +#elif defined (CONFIG_ESPRESSIF_FLASH_8M) +# define FLASH_SIZE 0x800000 +#elif defined (CONFIG_ESPRESSIF_FLASH_16M) +# define FLASH_SIZE 0x1000000 +#endif + +MEMORY +{ +#ifdef CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT + metadata (RX) : org = CONFIG_ESPRESSIF_APP_MCUBOOT_HEADER_SIZE, len = 0x60 + ROM (RX) : org = ORIGIN(metadata) + LENGTH(metadata), + len = FLASH_SIZE - ORIGIN(ROM) +#elif defined (CONFIG_ESPRESSIF_SIMPLE_BOOT) + ROM (RX) : org = ORIGIN(ROM), + len = FLASH_SIZE - ORIGIN(ROM) +#endif + + iram0_0_seg (RX) : org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE + +#ifdef CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT + irom0_0_seg (RX) : org = 0x42000000, len = FLASH_SIZE +#else + irom0_0_seg (RX) : org = 0x42000000, len = FLASH_SIZE +#endif + + dram0_0_seg (RW) : org = SRAM_DRAM_ORG, len = I_D_SRAM_SIZE + +#ifdef CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT + drom0_0_seg (R) : org = 0x3c000000 + ORIGIN(ROM), + len = FLASH_SIZE - ORIGIN(ROM) +#else + drom0_0_seg (R) : org = 0x3c000000, len = FLASH_SIZE +#endif + + rtc_iram_seg(RWX) : org = 0x50000000, len = 0x2000 - RESERVE_RTC_MEM + rtc_reserved_seg(RW) : org = 0x50000000 + 0x2000 - RESERVE_RTC_MEM, len = RESERVE_RTC_MEM +} + +REGION_ALIAS("rtc_data_seg", rtc_iram_seg ); +REGION_ALIAS("rtc_slow_seg", rtc_iram_seg ); +REGION_ALIAS("rtc_data_location", rtc_iram_seg ); + +#if CONFIG_ESPRESSIF_RUN_IRAM + REGION_ALIAS("default_rodata_seg", dram0_0_seg); + REGION_ALIAS("default_code_seg", iram0_0_seg); +#else + REGION_ALIAS("default_rodata_seg", drom0_0_seg); + REGION_ALIAS("default_code_seg", irom0_0_seg); +#endif /* CONFIG_ESPRESSIF_RUN_IRAM */ diff --git a/boards/risc-v/esp32c2/common/scripts/esp32c2_legacy_sections.ld b/boards/risc-v/esp32c2/common/scripts/esp32c2_legacy_sections.ld new file mode 100644 index 00000000000..95921576e58 --- /dev/null +++ b/boards/risc-v/esp32c2/common/scripts/esp32c2_legacy_sections.ld @@ -0,0 +1,297 @@ +/**************************************************************************** + * boards/risc-v/esp32c2/common/scripts/esp32c2_legacy_sections.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Default entry point: */ + +ENTRY(__start); + +SECTIONS +{ + .iram0.text : + { + _iram_start = ABSOLUTE(.); + + /* Vectors go to start of IRAM */ + + KEEP(*(.exception_vectors.text)); + . = ALIGN(4); + + *(.iram1) + *(.iram1.*) + + *libarch.a:brownout.*(.text .text.* .literal .literal.*) + *libarch.a:cpu.*(.text .text.* .literal .literal.*) + *libarch.a:gpio_hal.*(.text .text.* .literal .literal.*) + *libarch.a:periph_ctrl.*(.text .text.* .literal .literal.*) + *libarch.a:rtc_clk.*(.text .text.* .literal .literal.*) + *libarch.a:rtc_sleep.*(.text .text.* .literal .literal.*) + *libarch.a:rtc_time.*(.text .text.* .literal .literal.*) + *libarch.a:systimer.*(.text .text.* .literal .literal.*) + *libarch.a:systimer_hal.*(.text .text.* .literal .literal.*) + *libarch.a:uart_hal_iram.*(.text .text.* .literal .literal.*) + *libarch.a:wdt_hal_iram.*(.text .text.* .literal .literal.*) + *libsched.a:irq_dispatch.*(.text .text.* .literal .literal.*) + *libc.a:sq_remlast.*(.literal .text .literal.* .text.*) + } >iram0_0_seg + + /* This section is required to skip .iram0.text area because iram0_0_seg + * and dram0_0_seg reflect the same address space on different buses. + */ + + .dram0.dummy (NOLOAD): + { + . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start; + } >dram0_0_seg + + .noinit (NOLOAD): + { + /* This section contains data that is not initialized during load, + * or during the application's initialization sequence. + */ + + *(.noinit) + *(.noinit.*) + } >dram0_0_seg + + .dram0.data : + { + _sdata = ABSOLUTE(.); + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.data1) + __global_pointer$ = . + 0x800; + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + *(.jcr) + *(.dram1) + *(.dram1.*) + + *libarch.a:brownout.*(.rodata .rodata.*) + *libarch.a:cpu.*(.rodata .rodata.*) + *libarch.a:gpio_hal.*(.rodata .rodata.*) + *libarch.a:periph_ctrl.*(.rodata .rodata.*) + *libarch.a:rtc_clk.*(.rodata .rodata.*) + *libarch.a:rtc_sleep.*(.rodata .rodata.*) + *libarch.a:rtc_time.*(.rodata .rodata.*) + *libarch.a:systimer.*(.rodata .rodata.*) + *libarch.a:systimer_hal.*(.rodata .rodata.*) + *libarch.a:uart_hal_iram.*(.rodata .rodata.*) + *libarch.a:wdt_hal_iram.*(.rodata .rodata.*) + *libsched.a:irq_dispatch.*(.rodata .rodata.*) + . = ALIGN(4); + _edata = ABSOLUTE(.); + } >dram0_0_seg + + /* Shared RAM */ + + .dram0.bss (NOLOAD) : + { + . = ALIGN (8); + _sbss = ABSOLUTE(.); + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.share.mem) + *(.gnu.linkonce.b.*) + *(COMMON) + + . = ALIGN (8); + _ebss = ABSOLUTE(.); + } >dram0_0_seg + + .flash.text : + { + _stext = .; + + *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.fini.literal) + *(.fini) + *(.gnu.version) + _etext = .; + + /* Similar to _iram_start, this symbol goes here so it is + * resolved by addr2line in preference to the first symbol in + * the flash.text segment. + */ + + _flash_cache_start = ABSOLUTE(0); + } >default_code_seg + + .flash_rodata_dummy (NOLOAD): + { + /* Start at the same alignment constraint than .flash.text */ + + . = ALIGN(ALIGNOF(.flash.text)); + + /* Create an empty gap as big as .flash.text section */ + + . = . + SIZEOF(.flash.text); + + /* Prepare the alignment of the section above. Few bytes (0x20) must be + * added for the mapping header. + */ + + . = ALIGN(0x10000) + 0x20; + } >default_rodata_seg + + .flash.rodata : ALIGN(0x10) + { + _srodata = ABSOLUTE(.); + + *(.rodata) + *(.rodata.*) + + *(.srodata.*) + + *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table .gcc_except_table.*) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + . = (. + 3) & ~ 3; + __eh_frame = ABSOLUTE(.); + KEEP(*(.eh_frame)) + . = (. + 7) & ~ 3; + + /* C++ constructor and destructor tables: + * RISC-V GCC is configured with --enable-initfini-array so it emits an + * .init_array section instead. + */ + + _sinit = ABSOLUTE(.); + KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*)) + KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array)) + _einit = ABSOLUTE(.); + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + + /* C++ exception handlers table: */ + + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + _erodata = ABSOLUTE(.); + + /* Literals are also RO data. */ + + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + . = ALIGN(4); + } >default_rodata_seg + + /* Marks the end of IRAM code segment */ + + .iram0.text_end (NOLOAD) : + { + . = ALIGN (16); + } >iram0_0_seg + + .iram0.data : + { + . = ALIGN(16); + *(.iram.data) + *(.iram.data*) + } >iram0_0_seg + + .iram0.bss (NOLOAD) : + { + . = ALIGN(16); + *(.iram.bss) + *(.iram.bss*) + + . = ALIGN(16); + _iram_end = ABSOLUTE(.); + } >iram0_0_seg + + /* RTC fast memory holds RTC wake stub code !*/ + + .rtc.text : + { + . = ALIGN(4); + *(.rtc.literal .rtc.text) + } >rtc_iram_seg + + /* RTC BSS section. */ + + .rtc.bss (NOLOAD) : + { + *(.rtc.bss) + } >rtc_iram_seg + + /* RTC data section holds RTC wake stub data/rodata. */ + + .rtc.data : + { + *(.rtc.data) + *(.rtc.data.*) + *(.rtc.rodata) + *(.rtc.rodata.*) + } >rtc_iram_seg + + /* This section holds RTC data that should have fixed addresses. + * The data are not initialized at power-up and are retained during deep sleep. + */ + .rtc_reserved (NOLOAD): + { + . = ALIGN(4); + _rtc_reserved_start = ABSOLUTE(.); + /* New data can only be added here to ensure existing data are not moved. + Because data have adhered to the end of the segment and code is relied on it. + >> put new data here << */ + + *(.rtc_timer_data_in_rtc_mem .rtc_timer_data_in_rtc_mem.*) + KEEP(*(.bootloader_data_rtc_mem .bootloader_data_rtc_mem.*)) + _rtc_reserved_end = ABSOLUTE(.); + } > rtc_reserved_seg + + _rtc_reserved_length = _rtc_reserved_end - _rtc_reserved_start; + ASSERT((_rtc_reserved_length <= LENGTH(rtc_reserved_seg)), + "RTC reserved segment data does not fit.") + +} + diff --git a/boards/risc-v/esp32c2/common/scripts/esp32c2_sections.ld b/boards/risc-v/esp32c2/common/scripts/esp32c2_sections.ld new file mode 100644 index 00000000000..6818791ec32 --- /dev/null +++ b/boards/risc-v/esp32c2/common/scripts/esp32c2_sections.ld @@ -0,0 +1,640 @@ +/**************************************************************************** + * boards/risc-v/espressif/common/scripts/esp32c2_sections.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#include "common.ld" + +/* Default entry point: */ + +ENTRY(__start); + +SECTIONS +{ +#ifdef CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT + .metadata : + { + /* The following metadata refers to the to MCUboot's struct + * esp_image_load_header defined at the following commit: + * https://github.com/mcu-tools/mcuboot/blob/cd22b693da426826e0255f8ee5b18d7360d9bc8f/boot/espressif/hal/include/esp_mcuboot_image.h + */ + + /* Magic for load header */ + + LONG(0xace637d3) + + /* Application entry point address */ + + KEEP(*(.entry_addr)) + + /* IRAM metadata: + * - Destination address (VMA) for IRAM region + * - Flash offset (LMA) for start of IRAM region + * - Size of IRAM region + */ + + LONG(ADDR(.iram0.text)) + LONG(LOADADDR(.iram0.text)) + LONG(SIZEOF(.iram0.text)) + + /* DRAM metadata: + * - Destination address (VMA) for DRAM region + * - Flash offset (LMA) for start of DRAM region + * - Size of DRAM region + */ + + LONG(ADDR(.dram0.data)) + LONG(LOADADDR(.dram0.data)) + LONG(SIZEOF(.dram0.data)) + + /* RTC_IRAM metadata: + * - Destination address (VMA) for RTC_IRAM region + * - Flash offset (LMA) for start of RTC_IRAM region + * - Size of RTC_IRAM region + */ + + LONG(ADDR(.rtc.text)) + LONG(LOADADDR(.rtc.text)) + LONG(SIZEOF(.rtc.text)) + + /* RTC_DRAM metadata: + * - Destination address (VMA) for RTC_DRAM region + * - Flash offset (LMA) for start of RTC_DRAM region + * - Size of RTC_DRAM region + */ + + LONG(ADDR(.rtc.data)) + LONG(LOADADDR(.rtc.data)) + LONG(SIZEOF(.rtc.data)) + + /* IROM metadata: + * - Destination address (VMA) for IROM region + * - Flash offset (LMA) for start of IROM region + * - Size of IROM region + */ + + LONG(ADDR(.flash.text)) + LONG(LOADADDR(.flash.text)) + LONG(SIZEOF(.flash.text)) + + /* DROM metadata: + * - Destination address (VMA) for DROM region + * - Flash offset (LMA) for start of DROM region + * - Size of DROM region + */ + + LONG(ADDR(.flash.rodata)) + LONG(LOADADDR(.flash.rodata)) + LONG(LOADADDR(.flash.rodata) + SIZEOF(.flash.rodata) - LOADADDR(.flash.rodata)) + } >metadata +#endif + + .iram0.text : + { + _iram_start = ABSOLUTE(.); + + /* Vectors go to start of IRAM */ + + KEEP(*(.exception_vectors.text)); + . = ALIGN(4); + + *(.iram1) + *(.iram1.*) + + *libcoexist.a:(.coexiram .coexiram.*) + + *libpp.a:wifi_iram.*(.literal .text .literal.* .text.*) + *libpp.a:wifi_rx_iram.*(.literal .text .literal.* .text.*) + *libpp.a:wifi_extra_iram.*(.literal .text .literal.* .text.*) + *libpp.a:wifi_slp_iram.*(.literal .text .literal.* .text.*) + *libpp.a:wifi_or_slp_iram.*(.literal .text .literal.* .text.*) + *libpp.a:wifi_slp_rx_iram.*(.literal .text .literal.* .text.*) + + *libsched.a:irq_dispatch.*(.text .text.* .literal .literal.*) + *libsched.a:sched_lock.*(.text .text.* .literal .literal.*) + *libsched.a:sched_unlock.*(.text .text.* .literal .literal.*) + + *libarch.a:*(.text.esprv_intc_int_get_type .literal.esprv_intc_int_get_type) + *libarch.a:*riscv_doirq.*(.text .text.* .literal .literal.*) + *libarch.a:*brownout.*(.text .text.* .literal .literal.*) + *libarch.a:*cpu.*(.text .text.* .literal .literal.*) + *libarch.a:*gpio_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*periph_ctrl.*(.text .text.* .literal .literal.*) + *libarch.a:*clk.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_clk.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_clk_tree.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_clk_tree_common.*(.text .text.* .literal .literal.*) + *libarch.a:*clk_tree_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*rtc_init.*(.text .text.* .literal .literal.*) + *libarch.a:*regi2c_ctrl.*(.text .text.* .literal .literal.*) + *libarch.a:*gpio_periph.*(.text .text.* .literal .literal.*) + *libarch.a:*rtc_clk.*(.text .text.* .literal .literal.*) + *libarch.a:*rtc_clk_init.*(.text .text.* .literal .literal.*) + *libarch.a:*rtc_sleep.*(.text .text.* .literal .literal.*) + *libarch.a:*rtc_time.*(.text .text.* .literal .literal.*) + *libarch.a:*systimer.*(.text .text.* .literal .literal.*) + *libarch.a:*systimer_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*uart_hal_iram.*(.text .text.* .literal .literal.*) + *libarch.a:*wdt_hal_iram.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_banner_wrap.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_init.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_common.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_common_loader.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_console.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_console_loader.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_esp32c2.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_flash.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_flash_config_esp32c2.*(.text .text.* .literal .literal.*) + *libarch.a:*flash_qio_mode.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_clock_init.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_clock_loader.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_efuse.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_panic.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_mem.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_random.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_random_esp32c2.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_image_format.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_soc.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_sha.*(.text .text.* .literal .literal.*) + *libarch.a:*flash_encrypt.*(.text .text.* .literal .literal.*) + *libarch.a:*cache_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*uart_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*mpu_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*mmu_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*uart_periph.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_rom_uart.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_rom_sys.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_rom_spiflash.*(.text .text.* .literal .literal.*) + *libarch.a:*efuse_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*efuse_utility.*(.text .text.* .literal .literal.*) + *libarch.a:*apm_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*log.*(.text .text.* .literal .literal.*) + *libarch.a:*log_lock.*(.literal .literal.* .text .text.*) + *libarch.a:*log_print.*(.literal .literal.* .text .text.*) + *libarch.a:*log_timestamp.*(.literal.esp_log_early_timestamp .text.esp_log_early_timestamp) + *libarch.a:*log_timestamp.*(.literal.esp_log_timestamp .text.esp_log_timestamp) + *libarch.a:*log_timestamp_common.*(.literal .literal.* .text .text.*) + *libarch.a:*log_write.*(.literal.esp_log_write .text.esp_log_write) + *libarch.a:*log_write.*(.literal.esp_log_writev .text.esp_log_writev) + *libarch.a:*interrupt_intc.*(.literal .literal.* .text .text.*) + *libarch.a:esp_spiflash.*(.literal .text .literal.* .text.*) + *libarch.a:esp_flash_api.*(.text .text.* .literal .literal.*) + *libarch.a:esp_flash_spi_init.*(.text .text.* .literal .literal.*) + *libarch.a:spi_flash_hal_iram.*(.literal .literal.* .text .text.*) + *libarch.a:spi_flash_encrypt_hal_iram.*(.text .text.* .literal .literal.*) + *libarch.a:spi_flash_hal_gpspi.*(.literal .literal.* .text .text.*) + *libarch.a:spi_flash_chip*.*(.literal .literal.* .text .text.*) + *libarch.a:spi_flash_wrap.*(.literal .literal.* .text .text.*) + *libarch.a:spi_flash_os_func_noos.*(.literal .literal.* .text .text.*) + *libarch.a:spi_flash_os_func_app.*(.literal .literal.* .text .text.*) + *libarch.a:flash_brownout_hook.*(.literal .literal.* .text .text.*) + *libarch.a:esp_cache.*(.literal .literal.* .text .text.*) + *libarch.a:esp_cache_utils.*(.literal .literal.* .text .text.*) + *libarch.a:cache_utils.*(.literal .literal.* .text .text.*) + *libarch.a:memspi_host_driver.*(.literal .literal.* .text .text.*) + *libarch.a:critical_section.*(.literal .literal.* .text .text.*) + *libarch.a:os.*(.literal.nuttx_enter_critical .text.nuttx_enter_critical) + *libarch.a:os.*(.literal.nuttx_exit_critical .text.nuttx_exit_critical) + *libarch.a:*riscv_modifyreg32.*(.literal .literal.* .text .text.*) + *libarch.a:intr_alloc.*(.literal.esp_intr_get_intno .text.esp_intr_get_intno) + *libarch.a:intr_alloc.*(.literal.esp_intr_get_cpu .text.esp_intr_get_cpu) + *libarch.a:interrupt.*(.literal.intr_handler_get .text.intr_handler_get) + *libarch.a:interrupt.*(.literal.intr_handler_get_arg .text.intr_handler_get_arg) + *libarch.a:interrupt.*(.literal.intr_get_item .text.intr_get_item) + *libarch.a:interrupt.*(.literal.intr_handler_get_arg .text.intr_handler_get_arg) + *libarch.a:*sleep_modes.*(.literal.esp_sleep_pd_config* .text.esp_sleep_pd_config*) + *libarch.a:*sleep_modes.*(.literal.esp_sleep_sub_mode_force_disable* .text.esp_sleep_sub_mode_force_disable*) + + *libc.a:sq_remlast.*(.literal .text .literal.* .text.*) + + esp_head.*(.literal .text .literal.* .text.*) + esp_start.*(.literal .text .literal.* .text.*) + + *libesp_wifi.a:esp_adapter.*(.literal.coex_pti_get_wrapper .text.coex_pti_get_wrapper) + *libesp_wifi.a:wifi_netif.*(.literal.wifi_sta_receive .text.wifi_sta_receive) + *libesp_wifi.a:wifi_netif.*(.literal.wifi_transmit_wrap .text.wifi_transmit_wrap) + + *libhal.a:timer_hal.*(.literal.timer_hal_capture_and_get_counter_value .text.timer_hal_capture_and_get_counter_value) + + *(.wifi0iram .wifi0iram.*) + *(.wifirxiram .wifirxiram.*) + *(.wifislpiram .wifislpiram.*) + *(.wifiorslpiram .wifiorslpiram.*) + *(.wifislprxiram .wifislprxiram.*) + *(.wifiextrairam .wifiextrairam.*) + + } >iram0_0_seg AT > ROM + + /* This section is required to skip .iram0.text area because iram0_0_seg + * and dram0_0_seg reflect the same address space on different buses. + */ + + .dram0.dummy (NOLOAD): + { + . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start; + } >dram0_0_seg + + .noinit (NOLOAD): + { + /* This section contains data that is not initialized during load, + * or during the application's initialization sequence. + */ + . = ALIGN(4); + *(.noinit) + *(.noinit.*) + . = ALIGN(4) ; + } >dram0_0_seg + + .dram0.data : + { + . = ALIGN (16); + _data_start = ABSOLUTE(.); + _sdata = ABSOLUTE(.); + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.data1) + __global_pointer$ = . + 0x800; + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + *(.jcr) + *(.dram1) + *(.dram1.*) + + *libsched.a:irq_dispatch.*(.rodata .rodata.*) + *libsched.a:sched_lock.*(.rodata .rodata.*) + *libsched.a:sched_unlock.*(.rodata .rodata.*) + + *libarch.a:*(.rodata.esprv_intc_int_get_type) + *libarch.a:*riscv_doirq.*(.rodata .rodata.*) + *libarch.a:*brownout.*(.rodata .rodata.*) + *libarch.a:*cpu.*(.rodata .rodata.*) + *libarch.a:*gpio_hal.*(.rodata .rodata.*) + *libarch.a:*periph_ctrl.*(.rodata .rodata.*) + *libarch.a:*clk.*(.rodata .rodata.*) + *libarch.a:*esp_clk.*(.rodata .rodata.*) + *libarch.a:*esp_clk_tree.*(.rodata .rodata.*) + *libarch.a:*esp_clk_tree_common.*(.rodata .rodata.*) + *libarch.a:*clk_tree_hal.*(.rodata .rodata.*) + *libarch.a:*rtc_init.*(.rodata .rodata.*) + *libarch.a:*regi2c_ctrl.*(.rodata .rodata.*) + *libarch.a:*gpio_periph.*(.rodata .rodata.*) + *libarch.a:*rtc_clk.*(.rodata .rodata.*) + *libarch.a:*rtc_clk_init.*(.rodata .rodata.*) + *libarch.a:*rtc_sleep.*(.rodata .rodata.*) + *libarch.a:*rtc_time.*(.rodata .rodata.*) + *libarch.a:*systimer.*(.rodata .rodata.*) + *libarch.a:*systimer_hal.*(.rodata .rodata.*) + *libarch.a:*uart_hal_iram.*(.rodata .rodata.*) + *libarch.a:*wdt_hal_iram.*(.rodata .rodata.*) + *libarch.a:*bootloader_banner_wrap.*(.rodata .rodata.*) + *libarch.a:*bootloader_init.*(.rodata .rodata.*) + *libarch.a:*bootloader_common.*(.rodata .rodata.*) + *libarch.a:*bootloader_common_loader.*(.rodata .rodata.*) + *libarch.a:*bootloader_console.*(.rodata .rodata.*) + *libarch.a:*bootloader_console_loader.*(.rodata .rodata.*) + *libarch.a:*bootloader_esp32c2.*(.rodata .rodata.*) + *libarch.a:*bootloader_flash.*(.rodata .rodata.*) + *libarch.a:*bootloader_flash_config_esp32c2.*(.rodata .rodata.*) + *libarch.a:*flash_qio_mode.*(.rodata .rodata.*) + *libarch.a:*bootloader_clock_init.*(.rodata .rodata.*) + *libarch.a:*bootloader_clock_loader.*(.rodata .rodata.*) + *libarch.a:*bootloader_efuse.*(.rodata .rodata.*) + *libarch.a:*bootloader_panic.*(.rodata .rodata.*) + *libarch.a:*bootloader_mem.*(.rodata .rodata.*) + *libarch.a:*bootloader_random.*(.rodata .rodata.*) + *libarch.a:*bootloader_random_esp32c2.*(.rodata .rodata.*) + *libarch.a:*esp_image_format.*(.rodata .rodata.*) + *libarch.a:*bootloader_soc.*(.rodata .rodata.*) + *libarch.a:*bootloader_sha.*(.rodata .rodata.*) + *libarch.a:*flash_encrypt.*(.rodata .rodata.*) + *libarch.a:*cache_hal.*(.rodata .rodata.*) + *libarch.a:*uart_hal.*(.rodata .rodata.*) + *libarch.a:*mpu_hal.*(.rodata .rodata.*) + *libarch.a:*mmu_hal.*(.rodata .rodata.*) + *libarch.a:*uart_periph.*(.rodata .rodata.*) + *libarch.a:*esp_rom_uart.*(.rodata .rodata.*) + *libarch.a:*esp_rom_sys.*(.rodata .rodata.*) + *libarch.a:*esp_rom_spiflash.*(.rodata .rodata.*) + *libarch.a:*efuse_hal.*(.rodata .rodata.*) + *libarch.a:*efuse_utility.*(.rodata .rodata.*) + *libarch.a:*log.*(.rodata .rodata.*) + *libarch.a:*log_noos.*(.rodata .rodata.*) + *libarch.a:esp_spiflash.*(.rodata .rodata.*) + *libarch.a:esp_flash_api.*(.rodata .rodata.*) + *libarch.a:esp_flash_spi_init.*(.rodata .rodata.*) + *libarch.a:spi_flash_hal_iram.*(.rodata .rodata.*) + *libarch.a:spi_flash_encrypt_hal_iram.*(.rodata .rodata.*) + *libarch.a:spi_flash_hal_gpspi.*(.rodata .rodata.*) + *libarch.a:spi_flash_chip*.*(.rodata .rodata.*) + *libarch.a:spi_flash_wrap.*(.rodata .rodata.*) + *libarch.a:spi_flash_os_func_noos.*(.rodata .rodata.*) + *libarch.a:spi_flash_os_func_app.*(.rodata .rodata.*) + *libarch.a:flash_brownout_hook.*(.rodata .rodata.*) + *libarch.a:esp_cache.*(.rodata .rodata.*) + *libarch.a:esp_cache_utils.*(.rodata .rodata.*) + *libarch.a:cache_utils.*(.rodata .rodata.*) + *libarch.a:startup_funcs.*(.rodata .rodata.*) + *libarch.a:memspi_host_driver.*(.rodata .rodata.*) + *libarch.a:critical_section.*(.rodata .rodata.*) + *libarch.a:os.*(.rodata.g_int_flags_count .rodata.g_int_flags) + *libarch.a:*sleep_modes.*(.rodata.esp_sleep_pd_config*) + *libarch.a:*sleep_modes.*(.rodata.esp_sleep_sub_mode_force_disable*) + + esp_head.*(.rodata .rodata.*) + esp_start.*(.rodata .rodata.*) + + _edata = ABSOLUTE(.); + _data_end = ABSOLUTE(.); + . = ALIGN(4); + } >dram0_0_seg AT > ROM + + /* Shared RAM */ + + .dram0.bss (NOLOAD) : + { + . = ALIGN (8); + _bss_start = ABSOLUTE(.); + _sbss = ABSOLUTE(.); + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.share.mem) + *(.gnu.linkonce.b.*) + *(COMMON) + + . = ALIGN (8); + _ebss = ABSOLUTE(.); + _bss_end = ABSOLUTE(.); + } >dram0_0_seg + + _image_irom_vma = ADDR(.flash.text); + _image_irom_lma = LOADADDR(.flash.text); + _image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_lma; + + .flash.text : ALIGN(0xFFFF) + { + _stext = .; + _instruction_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.text start, this can be used for mmu driver to maintain virtual address */ + _text_start = ABSOLUTE(.); + + *(EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifi0iram EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifi0iram.*) + *(.wifiextrairam .wifiextrairam.*) + *(EXCLUDE_FILE(*libpp.a) .wifiorslpiram EXCLUDE_FILE(*libpp.a) .wifiorslpiram.*) + *(EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifirxiram EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifirxiram.*) + *(.wifislpiram .wifislpiram.*) + *(EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifislprxiram EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifislprxiram.*) + + *libesp_wifi.a:esp_adapter.*(.text .text.clear_intr_wrapper .text.coex_deinit_wrapper .text.coex_disable_wrapper .text.coex_enable_wrapper .text.coex_init_wrapper .text.coex_register_start_cb_wrapper .text.coex_schm_curr_period_get_wrapper .text.coex_schm_curr_phase_get_wrapper .text.coex_schm_flexible_period_get_wrapper .text.coex_schm_flexible_period_set_wrapper .text.coex_schm_interval_get_wrapper .text.coex_schm_process_restart_wrapper .text.coex_schm_register_cb_wrapper .text.co [...] + *libarch.a:*brownout.*(.text .text.*) + + *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.fini.literal) + *(.fini) + *(.gnu.version) + + . += 16; + + _text_end = ABSOLUTE(.); + _instruction_reserved_end = ABSOLUTE(.); /* This is a symbol marking the flash.text end, this can be used for mmu driver to maintain virtual address */ + _etext = .; + + /* Similar to _iram_start, this symbol goes here so it is + * resolved by addr2line in preference to the first symbol in + * the flash.text segment. + */ + + _flash_cache_start = ABSOLUTE(0); + } >default_code_seg AT > ROM + + .flash_rodata_dummy (NOLOAD) : ALIGN(0xFFFF) + { + /* Start at the same alignment constraint than .flash.text */ + + /* . = ALIGN(ALIGNOF(.flash.text)); */ + + /* Create an empty gap as big as .flash.text section */ + + . = . + SIZEOF(.flash.text); + + /* Prepare the alignment of the section above. Few bytes (0x20) must be + * added for the mapping header. + */ + + /*. = ALIGN(0x10000) + 0x20; */ + } >default_rodata_seg + + _image_drom_vma = ADDR(.flash.rodata); + _image_drom_lma = LOADADDR(.flash.rodata); + _image_drom_size = LOADADDR(.flash.rodata) + SIZEOF(.flash.rodata) - _image_drom_lma; + + .flash.appdesc : ALIGN(0x10) + { + _rodata_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.rodata start, this can be used for mmu driver to maintain virtual address */ + _rodata_start = ABSOLUTE(.); + + /* Create an empty gap within this section. Thanks to this, the end of this + * section will match .flash.rodata's begin address. Thus, both sections + * will be merged when creating the final bin image. */ + . = ALIGN(ALIGNOF(.flash.rodata)); + } >default_rodata_seg + + .flash.rodata : ALIGN(0xFFFF) + { + _srodata = ABSOLUTE(.); + *(EXCLUDE_FILE (*libarch.a:esp_spiflash.* esp_head.* esp_start.*) .rodata) + *(EXCLUDE_FILE (*libarch.a:esp_spiflash.* esp_head.* esp_start.*) .rodata.*) + + *(.rodata) + *(.rodata.*) + *(.rodata_wlog_verbose.*) + *(.rodata_wlog_debug.*) + *(.rodata_wlog_info.*) + *(.rodata_wlog_warning.*) + *(.rodata_wlog_error.*) + + *(.srodata.*) + + *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table .gcc_except_table.*) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + . = (. + 3) & ~ 3; + __eh_frame = ABSOLUTE(.); + KEEP(*(.eh_frame)) + . = (. + 7) & ~ 3; + + /* C++ constructor and destructor tables: + * RISC-V GCC is configured with --enable-initfini-array so it emits an + * .init_array section instead. + */ + + /* C++ exception handlers table: */ + + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + _erodata = ABSOLUTE(.); + + /* Literals are also RO data. */ + + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + + _sinit = ABSOLUTE(.); + + . = ALIGN(4); + __init_priority_array_start = ABSOLUTE(.); + KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*)) + __init_priority_array_end = ABSOLUTE(.); + + . = ALIGN(4); + __init_array_start = ABSOLUTE(.); + KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array)) + __init_array_end = ABSOLUTE(.); + + /* Addresses of memory regions reserved via SOC_RESERVE_MEMORY_REGION() */ + + . = ALIGN(4); + soc_reserved_memory_region_start = ABSOLUTE(.); + KEEP (*(.reserved_memory_address)) + soc_reserved_memory_region_end = ABSOLUTE(.); + + /* System init functions registered via ESP_SYSTEM_INIT_FN */ + + . = ALIGN(4); + _esp_system_init_fn_array_start = ABSOLUTE(.); + KEEP (*(SORT_BY_INIT_PRIORITY(.esp_system_init_fn.*))) + _esp_system_init_fn_array_end = ABSOLUTE(.); + + _einit = ABSOLUTE(.); + + } >default_rodata_seg AT > ROM + + .flash.rodata_noload (NOLOAD) : + { + /* + This is a symbol marking the flash.rodata end, this can be used for mmu driver to maintain virtual address + We don't need to include the noload rodata in this section + */ + _rodata_reserved_end = ABSOLUTE(.); + . = ALIGN (4); + } > default_rodata_seg AT > ROM + + /* Marks the end of IRAM code segment */ + + .iram0.text_end (NOLOAD) : + { + . = ALIGN (16); + } >iram0_0_seg + + .iram0.data : + { + . = ALIGN(16); + *(.iram.data) + *(.iram.data*) + } >iram0_0_seg + + .iram0.bss (NOLOAD) : + { + . = ALIGN(16); + *(.iram.bss) + *(.iram.bss*) + + . = ALIGN(16); + _iram_end = ABSOLUTE(.); + } >iram0_0_seg + + /* RTC fast memory holds RTC wake stub code !*/ + + .rtc.text : + { + . = ALIGN(4); + *(.rtc.literal .rtc.literal.*) + *(.rtc.text .rtc.text.*) + *(.rtc.entry.text) + . += 16; + . = ALIGN(4); + } > rtc_iram_seg AT > ROM + + /* RTC BSS section. */ + + .rtc.bss (NOLOAD) : + { + *(.rtc.bss) + } >rtc_iram_seg + + /* RTC data section holds RTC wake stub data/rodata. */ + + .rtc.data : + { + . = ALIGN(4); + *(.rtc.force_slow .rtc.force_slow.*) + *(.rtc.data) + *(.rtc.data.*) + *(.rtc.rodata) + *(.rtc.rodata.*) + } >rtc_iram_seg + + /* This section holds RTC data that should have fixed addresses. + * The data are not initialized at power-up and are retained during deep sleep. + */ + .rtc_reserved (NOLOAD): + { + . = ALIGN(4); + _rtc_reserved_start = ABSOLUTE(.); + /* New data can only be added here to ensure existing data are not moved. + Because data have adhered to the end of the segment and code is relied on it. + >> put new data here << */ + + *(.rtc_timer_data_in_rtc_mem .rtc_timer_data_in_rtc_mem.*) + KEEP(*(.bootloader_data_rtc_mem .bootloader_data_rtc_mem.*)) + _rtc_reserved_end = ABSOLUTE(.); + } > rtc_reserved_seg + + _rtc_reserved_length = _rtc_reserved_end - _rtc_reserved_start; + ASSERT((_rtc_reserved_length <= LENGTH(rtc_reserved_seg)), + "RTC reserved segment data does not fit.") + +} diff --git a/boards/risc-v/esp32c2/common/src/CMakeLists.txt b/boards/risc-v/esp32c2/common/src/CMakeLists.txt new file mode 100644 index 00000000000..b7b2785374d --- /dev/null +++ b/boards/risc-v/esp32c2/common/src/CMakeLists.txt @@ -0,0 +1,25 @@ +# ############################################################################## +# boards/risc-v/esp32c2/common/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS) + +target_sources(board PRIVATE ${SRCS}) diff --git a/boards/risc-v/esp32c2/common/src/Make.defs b/boards/risc-v/esp32c2/common/src/Make.defs new file mode 100644 index 00000000000..74821f85cfe --- /dev/null +++ b/boards/risc-v/esp32c2/common/src/Make.defs @@ -0,0 +1,29 @@ +############################################################################# +# boards/risc-v/esp32c2/common/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +ifeq ($(CONFIG_ARCH_BOARD_COMMON),y) + +DEPPATH += --dep-path src +VPATH += :src +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)src + +endif
