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commit 67eb7b1c3326087d04a1122832a25726f928792c Author: leocafonso <[email protected]> AuthorDate: Wed Sep 30 18:36:06 2026 -0700 Documentation/arm/ra8m1: Document the GPT timers and shield GPIO Describe the GPT timer support on the RA8M1 platform page and the Arduino shield header's D2-D13 GPIO mapping on the EK-RA8M1 board page, including the ek-ra8m1:timer-gpio configuration used to test them. Co-Authored-By: Claude Sonnet 5 <[email protected]> Assisted-by: Claude:claude-sonnet-5 Signed-off-by: leocafonso <[email protected]> --- .../platforms/arm/ra8m1/boards/ek-ra8m1/index.rst | 70 ++++++++++++++++++++++ Documentation/platforms/arm/ra8m1/index.rst | 30 ++++++++-- 2 files changed, 96 insertions(+), 4 deletions(-) diff --git a/Documentation/platforms/arm/ra8m1/boards/ek-ra8m1/index.rst b/Documentation/platforms/arm/ra8m1/boards/ek-ra8m1/index.rst index 1c001c38563..9ec46c21d4d 100644 --- a/Documentation/platforms/arm/ra8m1/boards/ek-ra8m1/index.rst +++ b/Documentation/platforms/arm/ra8m1/boards/ek-ra8m1/index.rst @@ -105,6 +105,41 @@ Without ``CONFIG_ARCH_LEDS``, the LEDs are available through the ``userled`` upper half at ``/dev/userleds`` (bit 0 = LED1, bit 1 = LED2, bit 2 = LED3), or individually through the ``ULEDIOC_SETLED`` ioctl. +Arduino Shield GPIO +==================== + +The Arduino Uno shield header's D2-D5 are wired as inputs and D6-D13 as +outputs, through the generic GPIO expander driver (``CONFIG_DEV_GPIO``): + + ==== ============= ========= ========== + Pin R7FA8M1AHECBD Direction Device + ==== ============= ========= ========== + D2 P906 Input /dev/gpio0 + D3 P907 Input /dev/gpio1 + D4 P905 Input /dev/gpio2 + D5 P601 Input /dev/gpio3 + D6 P602 Output /dev/gpio4 + D7 P908 Output /dev/gpio5 + D8 P909 Output /dev/gpio6 + D9 P603 Output /dev/gpio7 + D10 P413 Output /dev/gpio8 + D11 P411 Output /dev/gpio9 + D12 P410 Output /dev/gpio10 + D13 P412 Output /dev/gpio11 + ==== ============= ========= ========== + +D0/D1 are not registered here: they are SCI9's RXD9/TXD9 pins (see +`Serial Console`_ below). The inputs are plain floating inputs, with no +pull-up or pull-down. + +``src/ra8m1_gpio.c`` registers these pins with ``gpio_pin_register()``. +``apps/examples/gpio`` reads or writes any of them from ``nsh``: + +.. code-block:: console + + nsh> gpio /dev/gpio0 + nsh> gpio -o 1 /dev/gpio4 + Serial Console =============== @@ -120,6 +155,32 @@ SCI9: SCI9 is the serial console in the default configurations, at 115200 8N1. +Timers +====== + +Any of the GPT channels can be registered as a timer. The board registers +GPT0 (32-bit) as ``/dev/timer0`` and GPT9 (16-bit) as ``/dev/timer1`` when +``CONFIG_RA_GPT0_GPT`` and ``CONFIG_RA_GPT9_GPT`` are set (see the +``GPT`` section of the RA8M1 platform page). No pins are used. PCLKD, which +clocks the timers, is 120 MHz in this port. + +The ``timer-gpio`` configuration builds on ``nsh`` with both channels +enabled, the GPIO expander driver (see `Arduino Shield GPIO`_ above), and +``apps/examples/timer_gpio`` built in. Unlike ``apps/examples/timer``, +which only logs samples to the console, ``timer_gpio`` toggles a GPIO pin +once per timer period -- so the timer's actual accuracy can be checked +directly with an oscilloscope or logic analyzer on the pin, rather than +trusted from console output alone: + +.. code-block:: console + + nsh> timer_gpio -t /dev/timer0 -g /dev/gpio4 + +The period comes from ``CONFIG_EXAMPLES_TIMER_GPIO_INTERVAL`` (200 ms in +this configuration). Note that ``/dev/timer1`` (GPT9, 16-bit) tops out at +about 559 ms at this port's 120 MHz PCLKD: a period that fits +``/dev/timer0`` may return ``-ERANGE`` on ``/dev/timer1``. + Loading Code ============ @@ -165,3 +226,12 @@ nsh-leds Same as ``nsh``, but without ``ostest``, and enables the ``userled`` driver on ``/dev/userleds`` (``CONFIG_ARCH_LEDS`` is not set, so NuttX does not drive the LEDs itself; see `LEDs`_ above). + +timer-gpio +---------- + +Same as ``nsh``, but registers GPT0 and GPT9 as ``/dev/timer0`` and +``/dev/timer1``, enables the GPIO expander driver on the Arduino shield +header (see `Arduino Shield GPIO`_ above), and builds in +``apps/examples/gpio`` and ``apps/examples/timer_gpio`` (see `Timers`_ +above). diff --git a/Documentation/platforms/arm/ra8m1/index.rst b/Documentation/platforms/arm/ra8m1/index.rst index 11437e9b1c9..4eaffc24537 100644 --- a/Documentation/platforms/arm/ra8m1/index.rst +++ b/Documentation/platforms/arm/ra8m1/index.rst @@ -46,7 +46,7 @@ KINT No ELC No DTC No DMAC No -GPT No +GPT Yes Timer only: /dev/timerN (GPT0-7 32-bit, GPT8-13 16-bit) AGT No RTC No WDT No @@ -95,13 +95,35 @@ GPIO Pins can be configured/operated using ``ra_gpio_*`` functions. +GPT +--- + +The General PWM Timer (GPT) has 8 32-bit channels (GPT0-7) and 6 16-bit +channels (GPT8-13). NuttX uses a channel as a generic timer, registered as +``/dev/timerN`` through the upper-half timer driver (``CONFIG_TIMER``): the +channel counts up in saw-wave PWM mode, with the clock taken from PCLKD +divided by the smallest of 1, 2, 4, 8, 16, 32, 64, 256 or 1024 that fits the +requested timeout, and the overflow interrupt is the timer expiry. The +PWM, capture, dead time and ELC/hardware trigger functions are not +supported. + +Each channel is enabled with ``CONFIG_RA_GPTn_GPT`` (under +``CONFIG_RA_GPT_TIMER``) and registered by the board with +``ra_gpt_timer_initialize()``. The timeout is set with +``TCIOC_SETTIMEOUT`` in microseconds and can be changed while the timer is +running. The longest timeout is about 4295 s on a 32-bit channel, and +about 559 ms on a 16-bit channel at a PCLKD of 120 MHz. + ICU --- The Interrupt Controller Unit routes peripheral events to NVIC vectors: -any event can be routed to any of its IELSR slots. NuttX assigns SCI_B -events to fixed slots (four per channel) and calls ``ra_attach_icu()`` at -start-up to route the enabled channels' events into them. +any event can be routed to any of its IELSR slots. NuttX gives each event +that an enabled peripheral needs a slot, packed from the first slot in the +order they are listed in ``ra8m1_irq.h``, so only the events of the +peripherals a build enables use a slot: four for each SCI_B UART, and one +(the counter overflow) for each GPT channel. ``ra_attach_icu()`` calls at +start-up route those events into their slots. Supported Boards =================
