daniel-p-carvalho opened a new pull request, #20448: URL: https://github.com/apache/nuttx/pull/20448
*Note: Please adhere to [Contributing Guidelines](https://github.com/apache/nuttx/blob/master/CONTRIBUTING.md).* ## Summary Initial support for the Microchip PIC32MZ-W1 family (WFI32E01PE module, PIC32MZ1025W104132 die) and a board port for the EV49N51A (Ethernet to Wi-Fi Bridge) reference design. This is opened as a **draft** to ask for review of one specific question before the rest of the port is polished: some register addresses, values and sequences needed to start the clocks and the power management unit could not be found in any public Microchip document. They were taken from Microchip's example firmware. Details are in the "Provenance of hardware facts" section below. What is included: - `arch/mips/src/pic32mz`: PIC32MZ-W1 memory map, IRQ vectors, PPS tables and feature headers (from the PIC32MZ-W_DFP, Apache-2.0). The W1 SFR layout differs from the EC/EF families already supported, so these are new files selected by `CONFIG_ARCH_CHIP_PIC32MZW1`. - `pic32mz_wfi32_pwrclk.c`: PMU and clock bring-up. Unlike EC/EF, W1 does not configure its PLLs from the configuration words; software must start the primary oscillator, program the system and Ethernet/Wi-Fi PLLs and switch SYSCLK itself. - W1-specific fixes in shared code: PRECON (PREFEN only accepts 0/1), PB6DIV is not written (it clocks the CPU on W1), UART1/2 baud rate from PBCLK3. - Configuration words (DEVCFG0/1/2/4, FBCFG0, FCPN0, FSIGN0) emitted by the build, configurable through Kconfig. - New Kconfig options: `PIC32MZ_W1_PMU_MLDO`, `PIC32MZ_W1_FLASH_WAITSTATES`, `PIC32MZ_W1_BOOTTRACE` (early boot trace on UART1, bring-up aid). - Board `ev49n51a` with an `nsh` configuration (console on UART1, dedicated pins RA8/RA9). - A separate commit fixes pre-existing nxstyle errors in `pic32mz_serial.c` (indentation only, no functional change), so that the file passes `checkpatch.sh`. ## Hardware The port was developed and tested on a custom board derived from the EV49N51A design (schematic 02-01134 Rev 2). The WFI32E01PE module (which contains the 40 MHz crystal), the debug UART and ICSP connections and the Ethernet PHY (LAN8720A, RMII) are the same as on the EV49N51A. The differences are limited to power and I/O circuitry the `nsh` configuration does not use: | | EV49N51A | Custom board | |---|---|---| | Power input | USB Type-C (5 V) or 3.3 V header | 24 V input, LMR51430 buck to 5 V | | 3.3 V rail | MCP1727 | MCP1727 (same) | | User LEDs | Red and green on RK1/RK3 | Not fitted | | Switches | SW201-SW203 | Not fitted | | GPIO headers, battery status header | Fitted | Not fitted | | 32.768 kHz SOSC crystal (X401) | Fitted | Not fitted | | Debug UART header (U1RX RA8 / U1TX RA9) | Fitted | Fitted | | ICSP header (PGC2/PGD2) | Fitted | Fitted | | Ethernet PHY and RJ45 | Fitted | Fitted | The board code drives the two user LEDs on RK1/RK3 as on the EV49N51A; on the custom board those pins are left unconnected. ## Provenance of hardware facts All files in this PR carry the Apache-2.0 header. The sources used are tagged in the code comments: - `[DS]`: PIC32MZ W1 and WFI32E01 Family Data Sheet, DS70005425P. - `[DFP]`: Microchip PIC32MZ-W_DFP 1.12.356 (Apache-2.0). - `[EX]`: not found in `[DS]` or `[DFP]`. Taken from Microchip's `WFI32_Ethernet_Wi-Fi_Bridge_OOB` example firmware (`pmu_init.c`, `plib_clk.c`, `initialization.c`). The example firmware is distributed under Microchip's own license, not Apache-2.0. No code was copied from it: `pic32mz_wfi32_pwrclk.c` and `hardware/pic32mzw1_pmuclk.h` are an independent implementation, and only hardware facts (register addresses, bit positions, values and the order in which the hardware needs them) were taken from the example, because we did not find them in any public document. Locations marked `[EX]`: | Location | Fact taken from the example | |---|---| | `hardware/pic32mzw1_pmuclk.h`: `PMUSPICTRL_CMD` | Meaning of bit 24 (1 = read) | | `hardware/pic32mzw1_pmuclk.h`: `PMUCLKCTRL_*` | Source-select encodings (field layout is in the DFP) | | `hardware/pic32mzw1_pmuclk.h`: `PMU_BUCKCFG1`..`PMU_MLDOCFG2` | Addresses 0x14-0x18 of the regulator-internal registers | | `hardware/pic32mzw1_pmuclk.h`: `PIC32MZ_OTP_*` | Location of the regulator factory trims (0x1FC55FE8-0x1FC55FFC); DS Table 35-2 note 2 refers to them without an address | | `hardware/pic32mzw1_pmuclk.h`: `PIC32MZ_RFSPICTL` | Register at 0xBF8C8028 and its bit layout (serial interface to the crystal oscillator analog front end) | | `hardware/pic32mzw1_pmuclk.h`: `PIC32MZ_PLLDBG` | Register at 0xBF8000E0 (PLL lock status), used on A1 silicon only | | `pic32mz_wfi32_pwrclk.c`: `WFI32_EWPLLCON`, `WFI32_CFGCON3` | Ethernet/Wi-Fi PLL divider values and initial RST/PWDN state | | `pic32mz_wfi32_pwrclk.c`: `WFI32_PMUCLKCTRL` | PMU interface clock values | | `pic32mz_wfi32_pwrclk.c`: `WFI32_DEF_*` | Regulator values used when the factory trim words are blank | | `pic32mz_wfi32_pwrclk.c`: `enum wfi32_silicon_e` | DEVID part numbers for the A1, B0 and G silicon revisions | | `pic32mz_wfi32_pwrclk.c`: `g_xosc_cfg_*`, `g_xosc_post_a` | Crystal oscillator setup written through RFSPICTL (addresses 0x85, 0x84, 0x1E, 0x82) | | `pic32mz_wfi32_pwrclk.c`: `wfi32_pmu_xfer()` | 5 us delay before polling SPIRDY | | `pic32mz_wfi32_pwrclk.c`: `wfi32_pmu_b0()`, `wfi32_pmu_mldo()` | Which regulator-internal registers are written, their values, and the adjustments for untrimmed parts | | `pic32mz_wfi32_pwrclk.c`: `wfi32_clk_a1()` | Ordering and delays of the A1 clock bring-up | | `pic32mz_lowinit.c`: `CONFIG_PIC32MZ_W1_FLASH_WAITSTATES` | Default of 5 flash wait states at 200 MHz (DS70005425 has no SYSCLK-to-PFMWS table) | With the `nsh` configuration (`CONFIG_PIC32MZ_W1_PMU_MLDO=y`, the regulator stays in its power-on MLDO mode), the `[EX]` items used at run time on B0 silicon are the crystal oscillator setup, the Ethernet/Wi-Fi PLL values and the flash wait-state default. We would welcome guidance from the reviewers on whether this approach is acceptable for the project, or what else would be needed. ## Impact - New chip family and new board only. The changes to shared PIC32MZ files are guarded by `CONFIG_ARCH_CHIP_PIC32MZW1`; EC/EF builds are unchanged. - Builds with the toolchain used by CI (Pinguino p32-gcc, `CONFIG_MIPS32_TOOLCHAIN_PINGUINOL`) and with Microchip XC32 v6.00. Known limitations / not yet done: - Switching the regulator from MLDO to buck mode on B0 silicon resets the device on our board, so the `nsh` configuration keeps MLDO mode. Under investigation. - SPI and I2C drivers still assume PBCLK2; on W1 they are clocked from PBCLK3 (I2C1 from PBCLK2). Not enabled in any configuration yet. - No Ethernet or Wi-Fi support. - Documentation page for the board is not written yet. ## Testing Host: Ubuntu Linux x86_64, Pinguino p32-gcc 4.9.2 and MPLAB XC32 v6.00. Target: custom board derived from EV49N51A (see "Hardware"), WFI32E01PE, silicon B0 (DEVID 0x0A400000). Programmed with a PICkit 3 through MPLAB IPE (`ipecmd -P32MZ1025W104132 -TPPK3`). Console on UART1, 115200 8N1. ``` ./tools/configure.sh -l ev49n51a:nsh make ``` Both toolchains: image boots to NSH; readback of the configuration words matches the build. `./tools/checkpatch.sh -c -u -m -g` passes on all commits. Log below is from the Pinguino build: ``` nsh> uname -a NuttX 13.0.1-RC1 5952a686f9 Oct 3 2026 14:06:52 mips ev49n51a nsh> free total used free maxused maxfree nused nfree name 122016 5864 116152 6792 115592 22 2 Umem nsh> ps TID PID PPID PRI POLICY TYPE NPX STATE EVENT SIGMASK STACK COMMAND 0 0 0 0 FIFO Kthread - Ready 0000000000000000 0002024 Idle_Task 2 2 0 100 RR Task - Running 0000000000000000 0002004 nsh_main nsh> sleep 2 nsh> uptime 00:00:06 up 0:00, load average: 0.00, 0.00, 0.00 ``` -- This is an automated message from the Apache Git Service. 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