daniel-p-carvalho opened a new pull request, #20454:
URL: https://github.com/apache/nuttx/pull/20454
## Summary
* `arch/mips/mips32: fix the L1 cache maintenance functions.`
* `arch/mips/pic32mz: initialize both L1 caches when KSEG0 is cacheable.`
The MIPS32 L1 cache support (`CONFIG_MIPS32_ICACHE` / `CONFIG_MIPS32_DCACHE`)
could not be used on PIC32MZ. I hit these bugs while enabling the caches on
the PIC32MZ-W1 (port in draft PR #20448).
`mips_cache.S`:
* The range functions rounded the end address down instead of up and
stopped before it, so the last line was never handled. A range inside a
single line (for example a 16-byte DMA descriptor) started a loop that
only ended when the address wrapped around 4 GB, which took seconds. With
the caches enabled, the PIC32MZ Ethernet driver stalled the system this
way.
* `HIT_WRITEBACK_D` was 0x15, which is Hit_Writeback_Inv_D; Hit_Writeback_D
is 0x19. `up_clean_dcache()` now uses Hit_Writeback_D and
`up_flush_dcache()` uses Hit_Writeback_Inv_D.
* The `*_all` functions used Hit operations over a KSEG0 range the size of
the cache, which only affects the lines caching that range. They now use
index operations (Index_Invalidate_I, Index_Writeback_Inv_D, and
Index_Store_Tag_D with a zero tag to discard the D-Cache).
* With `CONFIG_MIPS32_CACHE_AUTOINFO` the line size was computed with a
right shift instead of a left shift.
* The `CACHE_OP` loop label was `1`, the same label the callers use to skip
the operation, and the branch delay slot was left to whatever instruction
followed.
* `up_coherent_dcache()` called `up_invalidate_icache_all()` even when it is
not built.
`pic32mz_head.S` / Kconfig:
* `Config.K0` sets the cache algorithm for both caches, but the startup code
only initialized the tags of the caches selected in Kconfig. With only
`MIPS32_ICACHE`, the D-Cache ran with indeterminate tags. Both tag arrays
are now initialized whenever K0 is made cacheable (the XC32 startup code
does the same), with a hazard barrier after writing `Config`.
* `MIPS32_ICACHE` now selects `MIPS32_DCACHE` when the chip has one, so the
D-Cache maintenance needed for DMA is built whenever the D-Cache is in use.
## Impact
* Only configurations with `CONFIG_MIPS32_ICACHE` or `CONFIG_MIPS32_DCACHE`
are affected. No in-tree defconfig enables them, so existing boards are
unchanged.
* Selecting `MIPS32_ICACHE` now also enables `MIPS32_DCACHE` on chips that
have a D-Cache (the hardware enables both anyway).
* Note that all in-tree PIC32MZ linker scripts place the data memory in
KSEG1, so the D-Cache is only used for data if a board links it in KSEG0.
## Testing
* checkpatch: `./tools/checkpatch.sh -c -u -m -g upstream/master..HEAD`
passes.
* Build (Pinguino p32-gcc 4.9.2, as in CI): `pic32mz-starterkit:nsh`,
`chipkit-wifire:nsh`, `flipnclick-pic32mz:nsh`,
`flipnclick-pic32mz:nxlines` (only the existing `#warning` in
pic32mz_spi.c), plus `pic32mz-starterkit:nsh` with `CONFIG_MIPS32_ICACHE`,
with and without `CONFIG_MIPS32_CACHE_AUTOINFO`.
* Hardware: PIC32MZ-W1 (WFI32E01PE, B0 silicon) on the EV49N51A, with these
commits on top of the port in #20448, both caches enabled and the data
memory linked in KSEG0, using the Ethernet driver with D-Cache maintenance
(separate PR #20451):
* CoreMark (XC32 v6.00, -O2): 82.5 iterations/s without cache, 544.6 with
both caches.
* 5000 pings of 1472 bytes at 2 ms intervals with payload checking,
ifdown/ifup cycles and telnet sessions, no errors.
* Not tested on PIC32MZ EC/EF hardware.
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