This is an automated email from the ASF dual-hosted git repository.

acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git


The following commit(s) were added to refs/heads/master by this push:
     new 7fff8b746be arch/arm/src/imx9: add GPIO5 base address for i.MX95
7fff8b746be is described below

commit 7fff8b746bea074ab9b49d27b9924ed308dc9c5d
Author: Peter van der Perk <[email protected]>
AuthorDate: Tue Oct 6 17:22:04 2026 +0200

    arch/arm/src/imx9: add GPIO5 base address for i.MX95
    
    The i.MX95 has five GPIO instances, but g_gpio_base[] only listed the
    first four.  IMX9_GPIO_BASE(n) indexes this table directly, so any
    access to port GPIO5 read one element past the end of the array and
    caused a crash.
    
    The table was previously selected on CONFIG_ARCH_CHIP_IMX9_CORTEX_M,
    which covers both the i.MX93 M33 and the i.MX95 M7.  Since the i.MX93
    only has four GPIO instances and does not define IMX9_GPIO5_BASE, key
    the five entry table off CONFIG_ARCH_CHIP_IMX95_M7 and keep the four
    entry table for the i.MX93 (both the Cortex-A CONFIG_ARCH_CHIP_IMX93
    and the Cortex-M CONFIG_ARCH_CHIP_IMX93_M33 variants).
    
    Signed-off-by: Peter van der Perk <[email protected]>
---
 arch/arm/src/imx9/imx9_gpiobase.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/arch/arm/src/imx9/imx9_gpiobase.c 
b/arch/arm/src/imx9/imx9_gpiobase.c
index a6a793e2195..3d85729dd0b 100644
--- a/arch/arm/src/imx9/imx9_gpiobase.c
+++ b/arch/arm/src/imx9/imx9_gpiobase.c
@@ -33,8 +33,10 @@
  * Public Data
  ****************************************************************************/
 
-#if defined(CONFIG_ARCH_CHIP_IMX93)
-/* Base address for the GPIO memory mapped registers */
+#if defined(CONFIG_ARCH_CHIP_IMX95_M7)
+/* Base address for the GPIO memory mapped registers.  The i.MX95 has five
+ * GPIO instances.
+ */
 
 const uintptr_t g_gpio_base[] =
 {
@@ -42,9 +44,12 @@ const uintptr_t g_gpio_base[] =
   IMX9_GPIO2_BASE,
   IMX9_GPIO3_BASE,
   IMX9_GPIO4_BASE,
+  IMX9_GPIO5_BASE,
 };
-#elif defined(CONFIG_ARCH_CHIP_IMX9_CORTEX_M)
-/* Base address for the GPIO memory mapped registers */
+#elif defined(CONFIG_ARCH_CHIP_IMX93) || defined(CONFIG_ARCH_CHIP_IMX93_M33)
+/* Base address for the GPIO memory mapped registers.  The i.MX93 has four
+ * GPIO instances.
+ */
 
 const uintptr_t g_gpio_base[] =
 {

Reply via email to