daniel-p-carvalho opened a new pull request, #20524:
URL: https://github.com/apache/nuttx/pull/20524
## Summary
Ethernet support for the PIC32MZ-W1 (WFI32E01) and the EV49N51A board,
added in #20448. The common PIC32MZ Ethernet driver fixes this depends on
are already upstream (#20450, #20451, #20453, #20454).
Commits:
1. **arch/mips/pic32mz: add Ethernet support for PIC32MZ-W1.** The W1 only
has RMII and no DEVCFG3, so `PIC32MZ_FMIIEN`/`PIC32MZ_FETHIO` are hidden
and `CONFIG_PIC32MZ_FMIIEN` is 0 (RMII). With the old default of 1 (MII)
the driver skipped the RMII reset and speed setup. ETH_CLK_OUT (the 50 MHz
RMII reference clock from the Ethernet/Wi-Fi PLL) is enabled only when
the MAC is used; new `PIC32MZ_W1_ETH_EXTREFCLK` for boards with an
external 50 MHz oscillator.
2. **boards/mips/pic32mz/ev49n51a: add Ethernet support.** LAN8720A reset
(RA14) at boot, MDC divider, new `netnsh` configuration (Ethernet, IPv4,
TCP, UDP, ICMP, ping, telnetd; locally administered MAC, since the W1
has no factory MAC address), documentation.
3. **arch/mips/pic32mz: fix nxstyle issues in pic32mz_gpioirq.c.** No
functional change (needed because checkpatch checks the whole file).
4. **arch/mips/pic32mz: support GPIO interrupts on the PIC32MZ-W1.** The
change notification code assumed the EC/EF layout (IRQ = PORTA + index,
ports A-K). The W1 has PORTA/B/C/K with vectors CNA/CNB/CNC/CNK, and the
addresses of the missing ports belong to other peripherals (I2C1 is at
the PORTE address). Port index -> IRQ table on the W1, unimplemented
ports skipped, port index passed as the handler argument.
5. **boards/mips/pic32mz/ev49n51a: add the LAN8720A link interrupt.**
`CONFIG_EV49N51A_PHY_INTERRUPT` (default n) provides `arch_phy_irq()` on
RK6 (nINT). nINT reaches RK6 only through R309, not fitted on the kit.
6. **boards/mips/pic32mz/ev49n51a: enable the L1 caches.** I- and D-Cache
in nsh and netnsh, data in KSEG0, `BOARD_LOOPSPERMSEC` recalibrated.
CoreMark 82.5 -> 544.6 iterations/s (XC32).
## Impact
* PIC32MZ-W1 / EV49N51A only, except commit 4, which keeps the EC/EF code
path unchanged (build-tested on pic32mz-starterkit with PORTA/B/J
interrupts enabled).
* New board option `EV49N51A_PHY_INTERRUPT`, new arch option
`PIC32MZ_W1_ETH_EXTREFCLK` (both default n), new `ev49n51a:netnsh`.
* Documentation: EV49N51A board page (Ethernet, RMII clock, PHY interrupt,
L1 cache, netnsh).
* Promiscuous mode for this driver is a separate PR (#20517).
## Testing
Hardware built from the EV49N51A design (WFI32E01PE, silicon B0, LAN8720A
PHY, RMII clock from ETH_CLK_OUT), host Ubuntu Linux x86_64 with a USB
Ethernet adapter. Both toolchains (XC32 v6.00 and Pinguino GCC 4.9.2).
* `netnsh`: ping 64 B and 1400 B, 500 pings at 5 ms with 0% loss, 5000
pings of 1472 B at 2 ms with payload checking (caches on), telnet NSH
sessions, DHCP client against dnsmasq.
* Link: host forced to 10HD/10FD/100HD/100FD with autonegotiation; all
modes OK and the MAC follows the PHY (EMAC1CFG2/SUPP vs LAN8720A reg 31).
* `EV49N51A_PHY_INTERRUPT` + `NETINIT_MONITOR` (nINT wired to RK6): cable
unplug -> eth0 down in ~4 s, replug -> running in ~2 s; boot without
cable then plug; repeated ifdown/ifup.
* CoreMark and ping round trip before/after the caches:
| | caches off | caches on |
|---|---|---|
| CoreMark (XC32 -O2) | 82.5 it/s | 544.6 it/s |
| ping 64 B avg | 0.74 ms | 0.56 ms |
| ping 1400 B avg | 1.92 ms | 0.93 ms |
Build checks: every commit builds `ev49n51a:nsh` and `ev49n51a:netnsh` with
no warnings (bisectable); `./tools/checkpatch.sh -g` clean;
`refresh.sh ev49n51a:nsh ev49n51a:netnsh` leaves the defconfigs unchanged;
chipkit-wifire, flipnclick-pic32mz and pic32mz-starterkit still build.
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