This is an automated email from the ASF dual-hosted git repository. xiaoxiang781216 pushed a commit to branch master in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit 867367029426e806bfc54ddddb58f974aaa9ac27 Author: Afonso Oliveira <[email protected]> AuthorDate: Thu Oct 8 23:02:25 2026 +0100 Documentation/erbium: Describe the FCVT emulation. Explain that the four 64-bit integer conversions are emulated by default, what that costs in the emulator, which semantics the emulation follows, and which M-code instructions still stop the system. Assisted-by: Claude:claude-opus-5-5 Signed-off-by: Afonso Oliveira <[email protected]> --- .../platforms/risc-v/erbium/boards/minion/index.rst | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/Documentation/platforms/risc-v/erbium/boards/minion/index.rst b/Documentation/platforms/risc-v/erbium/boards/minion/index.rst index 7c0b98fd62b..301e0af1570 100644 --- a/Documentation/platforms/risc-v/erbium/boards/minion/index.rst +++ b/Documentation/platforms/risc-v/erbium/boards/minion/index.rst @@ -48,8 +48,7 @@ logic derives ``rv64imfc_zicsr_zifencei`` and ``lp64f`` from Kconfig. ET-Minion has no hardware for some instructions. Executing one raises exception 30, "M-code emulation": ``FDIV.S``, ``FSQRT.S``, ``FCVT.L.S``, ``FCVT.LU.S``, ``FCVT.S.L``, ``FCVT.S.LU``, ``FENCE.I``, ``SFENCE.VMA`` and -some ET packed instructions that GCC does not emit. NuttX reports the -exception, with the instruction in ``MTVAL``, and stops. +some ET packed instructions that GCC does not emit. The port compiles with ``-mno-fdiv``, so floating-point divide and square root use software helpers. GCC has no such option for the four 64-bit @@ -60,6 +59,16 @@ a 64-bit integer type such as ``long``, ``int64_t``, ``size_t`` or on ``expf()``, such as ``logf()``, ``powf()`` and the hyperbolic functions. +With ``CONFIG_ERBIUM_MCODE_EMULATION``, which is enabled by default when +the FPU is, the trap handler performs these four conversions in software +and resumes after the instruction. Each conversion then costs a trap, +about 260 instructions in ``erbium_emu``. The emulation follows the RISC-V +rules for rounding, saturation and floating-point flags. As ET-Minion does +for ``FCVT.W.S``, a subnormal input reads as zero and sets bit 31 of +``fflags``. Any other of these instructions, or a conversion when the +emulation is disabled, is reported as an exception, with the instruction +in ``MTVAL``, and stops the system. + Other single-precision instructions run in hardware, and FPU context switching works, including the FPU portion of ``ostest``. Double-precision arithmetic uses software. The atomic instruction extension is not enabled. @@ -77,7 +86,8 @@ To find these instructions in an image, search its disassembly:: In the ``nsh`` and ``ostest`` images, the only match is ``FENCE.I`` in the common ``riscv_fpuconfig`` routine, which Erbium does not call. Any other -match stops the system when it executes. +match stops the system when it executes, except the four conversions while +the emulation is enabled. Configurations ==============
