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new 250621172da boards/arm/stm32h7/stm32h735g-dk: Add Ethernet support.
250621172da is described below
commit 250621172da34284714f597776d69091d337be19
Author: raiden00pl <[email protected]>
AuthorDate: Mon Oct 12 16:34:02 2026 +0200
boards/arm/stm32h7/stm32h735g-dk: Add Ethernet support.
RMII pins for the on-board LAN8742A and a netnsh configuration.
Tested on stm32h735g-dk: 100 Mbps full-duplex link, ping both ways.
Assisted-by: Claude:claude-opus-5-5
Signed-off-by: raiden00pl <[email protected]>
---
.../arm/stm32h7/boards/stm32h735g-dk/index.rst | 5 ++
.../stm32h7/stm32h735g-dk/configs/netnsh/defconfig | 69 ++++++++++++++++++++++
boards/arm/stm32h7/stm32h735g-dk/include/board.h | 12 ++++
3 files changed, 86 insertions(+)
diff --git a/Documentation/platforms/arm/stm32h7/boards/stm32h735g-dk/index.rst
b/Documentation/platforms/arm/stm32h7/boards/stm32h735g-dk/index.rst
index c7b71568278..5fd76b8f226 100644
--- a/Documentation/platforms/arm/stm32h7/boards/stm32h735g-dk/index.rst
+++ b/Documentation/platforms/arm/stm32h7/boards/stm32h735g-dk/index.rst
@@ -46,3 +46,8 @@ mode with bit rate switching and internal loopback. Run
``can`` from NSH.
The FDCAN kernel clock is PLL2Q at 80 MHz. FDCAN1 is on PH13/PH14 and
FDCAN2 on PB6/PB5. FDCAN3 (PF7/PF6) needs SB29 and SB30 closed.
+
+netnsh
+------
+
+NuttShell with Ethernet (LAN8742A over RMII, PHY address 0).
diff --git a/boards/arm/stm32h7/stm32h735g-dk/configs/netnsh/defconfig
b/boards/arm/stm32h7/stm32h735g-dk/configs/netnsh/defconfig
new file mode 100644
index 00000000000..34a60b9660d
--- /dev/null
+++ b/boards/arm/stm32h7/stm32h735g-dk/configs/netnsh/defconfig
@@ -0,0 +1,69 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed
.config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that
includes your
+# modifications.
+#
+# CONFIG_STANDARD_SERIAL is not set
+CONFIG_ARCH="arm"
+CONFIG_ARCH_BOARD="stm32h735g-dk"
+CONFIG_ARCH_BOARD_STM32H735G_DK=y
+CONFIG_ARCH_CHIP="stm32h7"
+CONFIG_ARCH_CHIP_STM32=y
+CONFIG_ARCH_CHIP_STM32H735IG=y
+CONFIG_ARCH_CHIP_STM32H7=y
+CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y
+CONFIG_ARCH_INTERRUPTSTACK=2048
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARMV7M_DCACHE=y
+CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y
+CONFIG_ARMV7M_DTCM=y
+CONFIG_ARMV7M_ICACHE=y
+CONFIG_BOARD_LOOPSPERMSEC=66627
+CONFIG_BUILTIN=y
+CONFIG_DEBUG_SYMBOLS=y
+CONFIG_ETH0_PHY_LAN8742A=y
+CONFIG_FS_PROCFS=y
+CONFIG_INIT_ENTRYPOINT="nsh_main"
+CONFIG_INIT_STACKSIZE=4096
+CONFIG_INTELHEX_BINARY=y
+CONFIG_LINE_MAX=64
+CONFIG_MM_REGIONS=3
+CONFIG_NET=y
+CONFIG_NETDB_DNSCLIENT=y
+CONFIG_NET_ARP_IPIN=y
+CONFIG_NET_BROADCAST=y
+CONFIG_NET_ETH_PKTSIZE=1500
+CONFIG_NET_ICMP_SOCKET=y
+CONFIG_NET_LOOPBACK=y
+CONFIG_NET_ROUTE=y
+CONFIG_NET_STATISTICS=y
+CONFIG_NET_TCP=y
+CONFIG_NET_UDP=y
+CONFIG_NET_UDP_CHECKSUMS=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_READLINE=y
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_RAM_SIZE=327680
+CONFIG_RAM_START=0x24000000
+CONFIG_RAW_BINARY=y
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_HPWORK=y
+CONFIG_SCHED_LPWORK=y
+CONFIG_SCHED_WAITPID=y
+CONFIG_STM32_DTCMEXCLUDE=y
+CONFIG_STM32_ETHMAC=y
+CONFIG_STM32_PHYSR=31
+CONFIG_STM32_PHYSR_100FD=0x0018
+CONFIG_STM32_PHYSR_100HD=0x0008
+CONFIG_STM32_PHYSR_10FD=0x0014
+CONFIG_STM32_PHYSR_10HD=0x0004
+CONFIG_STM32_PHYSR_ALTCONFIG=y
+CONFIG_STM32_PHYSR_ALTMODE=0x001c
+CONFIG_STM32_PWR_DIRECT_SMPS_SUPPLY=y
+CONFIG_STM32_USART3=y
+CONFIG_SYSTEM_NSH=y
+CONFIG_SYSTEM_PING=y
+CONFIG_USART3_SERIAL_CONSOLE=y
diff --git a/boards/arm/stm32h7/stm32h735g-dk/include/board.h
b/boards/arm/stm32h7/stm32h735g-dk/include/board.h
index 739dd1fdd1d..dd449ef7eb7 100644
--- a/boards/arm/stm32h7/stm32h735g-dk/include/board.h
+++ b/boards/arm/stm32h7/stm32h735g-dk/include/board.h
@@ -203,6 +203,18 @@
#define GPIO_CAN3_RX (GPIO_CAN3_RX_2 | GPIO_SPEED_50MHz) /* PF6 */
#define GPIO_CAN3_TX (GPIO_CAN3_TX_2 | GPIO_SPEED_50MHz) /* PF7 */
+/* Ethernet: LAN8742A on RMII, PHY address 0. */
+
+#define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_1 | GPIO_SPEED_100MHz) /*
PB12 */
+#define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_1 | GPIO_SPEED_100MHz) /*
PB13 */
+#define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_1 | GPIO_SPEED_100MHz) /*
PB11 */
+#define GPIO_ETH_MDC (GPIO_ETH_MDC_0 | GPIO_SPEED_100MHz) /*
PC1 */
+#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0 | GPIO_SPEED_100MHz) /*
PA2 */
+#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0 | GPIO_SPEED_100MHz) /*
PC4 */
+#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0 | GPIO_SPEED_100MHz) /*
PC5 */
+#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0 | GPIO_SPEED_100MHz) /*
PA7 */
+#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0 | GPIO_SPEED_100MHz) /*
PA1 */
+
/* I2C4: touchscreen on PF14/PF15. */
#define STM32_RCC_D3CCIPR_I2C4SRC RCC_D3CCIPR_I2C4SEL_HSI
