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commit ccab492bfbfaadf032428d91710a1fca83b7a001 Author: raiden00pl <[email protected]> AuthorDate: Wed Aug 26 12:49:33 2026 +0200 arch/arm/stm32u5: Use the common GPDMA driver Select STM32_HAVE_IP_DMA_GPDMA and STM32_HAVE_DMA1 and provide the GPDMA instance parameters, the GPDMA1 request signal map taken from RM0456, and the USART RX DMA request numbers. DMA1 is the 16-channel GPDMA1 instance. The LPDMA1 instance uses a separate request numbering and is not supported yet. Signed-off-by: raiden00pl <[email protected]> Assisted-by: Claude Code --- arch/arm/src/stm32u5/Kconfig | 2 + arch/arm/src/stm32u5/chip.h | 7 + arch/arm/src/stm32u5/hardware/stm32_dmasigmap.h | 170 ++++++++++++++++++++++++ 3 files changed, 179 insertions(+) diff --git a/arch/arm/src/stm32u5/Kconfig b/arch/arm/src/stm32u5/Kconfig index bf8a4560bd3..5a99b0d4a76 100644 --- a/arch/arm/src/stm32u5/Kconfig +++ b/arch/arm/src/stm32u5/Kconfig @@ -10,6 +10,8 @@ comment "STM32U5 Configuration Options" config STM32_U5_PERIPHERALS bool default y + select STM32_HAVE_DMA1 + select STM32_HAVE_IP_DMA_GPDMA select STM32_HAVE_IP_EXTI_M33_V1 select STM32_HAVE_IP_GPIO_M33_V1 select STM32_HAVE_IP_TIMERS_V3 diff --git a/arch/arm/src/stm32u5/chip.h b/arch/arm/src/stm32u5/chip.h index 95117db4fdc..772ca5aadc8 100644 --- a/arch/arm/src/stm32u5/chip.h +++ b/arch/arm/src/stm32u5/chip.h @@ -50,4 +50,11 @@ #define ARMV8M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS +/* GPDMA instance parameters. DMA1 is the GPDMA1 instance; the LPDMA1 + * instance is not supported yet. + */ + +#define STM32_DMA1_NCHAN 16 +#define STM32_DMA1_IRQ_FIRST STM32_IRQ_GPDMA1_CH0 + #endif /* __ARCH_ARM_SRC_STM32U5_CHIP_H */ diff --git a/arch/arm/src/stm32u5/hardware/stm32_dmasigmap.h b/arch/arm/src/stm32u5/hardware/stm32_dmasigmap.h new file mode 100644 index 00000000000..112d400d493 --- /dev/null +++ b/arch/arm/src/stm32u5/hardware/stm32_dmasigmap.h @@ -0,0 +1,170 @@ +/**************************************************************************** + * arch/arm/src/stm32u5/hardware/stm32_dmasigmap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32_DMASIGMAP_H +#define __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32_DMASIGMAP_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* GPDMA1 request signals. The LPDMA1 instance uses a separate request + * numbering and is not supported yet. + */ + +#define GPDMA_REQ_ADC1 (0) +#define GPDMA_REQ_ADC4 (1) +#define GPDMA_REQ_DAC1_CH1 (2) +#define GPDMA_REQ_DAC1_CH2 (3) +#define GPDMA_REQ_TIM6_UP (4) +#define GPDMA_REQ_TIM7_UP (5) +#define GPDMA_REQ_SPI1_RX (6) +#define GPDMA_REQ_SPI1_TX (7) +#define GPDMA_REQ_SPI2_RX (8) +#define GPDMA_REQ_SPI2_TX (9) +#define GPDMA_REQ_SPI3_RX (10) +#define GPDMA_REQ_SPI3_TX (11) +#define GPDMA_REQ_I2C1_RX (12) +#define GPDMA_REQ_I2C1_TX (13) +#define GPDMA_REQ_I2C1_EVC (14) +#define GPDMA_REQ_I2C2_RX (15) +#define GPDMA_REQ_I2C2_TX (16) +#define GPDMA_REQ_I2C2_EVC (17) +#define GPDMA_REQ_I2C3_RX (18) +#define GPDMA_REQ_I2C3_TX (19) +#define GPDMA_REQ_I2C3_EVC (20) +#define GPDMA_REQ_I2C4_RX (21) +#define GPDMA_REQ_I2C4_TX (22) +#define GPDMA_REQ_I2C4_EVC (23) +#define GPDMA_REQ_USART1_RX (24) +#define GPDMA_REQ_USART1_TX (25) +#define GPDMA_REQ_USART2_RX (26) +#define GPDMA_REQ_USART2_TX (27) +#define GPDMA_REQ_USART3_RX (28) +#define GPDMA_REQ_USART3_TX (29) +#define GPDMA_REQ_UART4_RX (30) +#define GPDMA_REQ_UART4_TX (31) +#define GPDMA_REQ_UART5_RX (32) +#define GPDMA_REQ_UART5_TX (33) +#define GPDMA_REQ_LPUART1_RX (34) +#define GPDMA_REQ_LPUART1_TX (35) +#define GPDMA_REQ_SAI1_A (36) +#define GPDMA_REQ_SAI1_B (37) +#define GPDMA_REQ_SAI2_A (38) +#define GPDMA_REQ_SAI2_B (39) +#define GPDMA_REQ_OCTOSPI1 (40) +#define GPDMA_REQ_OCTOSPI2 (41) +#define GPDMA_REQ_TIM1_CH1 (42) +#define GPDMA_REQ_TIM1_CH2 (43) +#define GPDMA_REQ_TIM1_CH3 (44) +#define GPDMA_REQ_TIM1_CH4 (45) +#define GPDMA_REQ_TIM1_UP (46) +#define GPDMA_REQ_TIM1_TRIG (47) +#define GPDMA_REQ_TIM1_COM (48) +#define GPDMA_REQ_TIM8_CH1 (49) +#define GPDMA_REQ_TIM8_CH2 (50) +#define GPDMA_REQ_TIM8_CH3 (51) +#define GPDMA_REQ_TIM8_CH4 (52) +#define GPDMA_REQ_TIM8_UP (53) +#define GPDMA_REQ_TIM8_TRIG (54) +#define GPDMA_REQ_TIM8_COM (55) +#define GPDMA_REQ_TIM2_CH1 (56) +#define GPDMA_REQ_TIM2_CH2 (57) +#define GPDMA_REQ_TIM2_CH3 (58) +#define GPDMA_REQ_TIM2_CH4 (59) +#define GPDMA_REQ_TIM2_UP (60) +#define GPDMA_REQ_TIM3_CH1 (61) +#define GPDMA_REQ_TIM3_CH2 (62) +#define GPDMA_REQ_TIM3_CH3 (63) +#define GPDMA_REQ_TIM3_CH4 (64) +#define GPDMA_REQ_TIM3_UP (65) +#define GPDMA_REQ_TIM3_TRIG (66) +#define GPDMA_REQ_TIM4_CH1 (67) +#define GPDMA_REQ_TIM4_CH2 (68) +#define GPDMA_REQ_TIM4_CH3 (69) +#define GPDMA_REQ_TIM4_CH4 (70) +#define GPDMA_REQ_TIM4_UP (71) +#define GPDMA_REQ_TIM5_CH1 (72) +#define GPDMA_REQ_TIM5_CH2 (73) +#define GPDMA_REQ_TIM5_CH3 (74) +#define GPDMA_REQ_TIM5_CH4 (75) +#define GPDMA_REQ_TIM5_UP (76) +#define GPDMA_REQ_TIM5_TRIG (77) +#define GPDMA_REQ_TIM15_CH1 (78) +#define GPDMA_REQ_TIM15_UP (79) +#define GPDMA_REQ_TIM15_TRIG (80) +#define GPDMA_REQ_TIM15_COM (81) +#define GPDMA_REQ_TIM16_CH1 (82) +#define GPDMA_REQ_TIM16_UP (83) +#define GPDMA_REQ_TIM17_CH1 (84) +#define GPDMA_REQ_TIM17_UP (85) +#define GPDMA_REQ_DCMI_PSSI (86) +#define GPDMA_REQ_AES_IN (87) +#define GPDMA_REQ_AES_OUT (88) +#define GPDMA_REQ_HASH_IN (89) +#define GPDMA_REQ_UCPD1_TX (90) +#define GPDMA_REQ_UCPD1_RX (91) +#define GPDMA_REQ_MDF1_FLT0 (92) +#define GPDMA_REQ_MDF1_FLT1 (93) +#define GPDMA_REQ_MDF1_FLT2 (94) +#define GPDMA_REQ_MDF1_FLT3 (95) +#define GPDMA_REQ_MDF1_FLT4 (96) +#define GPDMA_REQ_MDF1_FLT5 (97) +#define GPDMA_REQ_ADF1_FLT0 (98) +#define GPDMA_REQ_FMAC_READ (99) +#define GPDMA_REQ_FMAC_WRITE (100) +#define GPDMA_REQ_CORDIC_READ (101) +#define GPDMA_REQ_CORDIC_WRITE (102) +#define GPDMA_REQ_SAES_IN (103) +#define GPDMA_REQ_SAES_OUT (104) +#define GPDMA_REQ_LPTIM1_IC1 (105) +#define GPDMA_REQ_LPTIM1_IC2 (106) +#define GPDMA_REQ_LPTIM1_UE (107) +#define GPDMA_REQ_LPTIM2_IC1 (108) +#define GPDMA_REQ_LPTIM2_IC2 (109) +#define GPDMA_REQ_LPTIM2_UE (110) +#define GPDMA_REQ_LPTIM3_IC1 (111) +#define GPDMA_REQ_LPTIM3_IC2 (112) +#define GPDMA_REQ_LPTIM3_UE (113) +#define GPDMA_REQ_HSPI1 (114) +#define GPDMA_REQ_I2C5_RX (115) +#define GPDMA_REQ_I2C5_TX (116) +#define GPDMA_REQ_I2C5_EVC (117) +#define GPDMA_REQ_I2C6_RX (118) +#define GPDMA_REQ_I2C6_TX (119) +#define GPDMA_REQ_I2C6_EVC (120) +#define GPDMA_REQ_USART6_RX (121) +#define GPDMA_REQ_USART6_TX (122) +#define GPDMA_REQ_ADC2 (123) +#define GPDMA_REQ_JPEG_RX (124) +#define GPDMA_REQ_JPEG_TX (125) + +/* USART RX DMA request numbers */ + +#define STM32_LPUART1_RXDMA_REQ GPDMA_REQ_LPUART1_RX +#define STM32_USART1_RXDMA_REQ GPDMA_REQ_USART1_RX +#define STM32_USART2_RXDMA_REQ GPDMA_REQ_USART2_RX +#define STM32_USART3_RXDMA_REQ GPDMA_REQ_USART3_RX +#define STM32_UART4_RXDMA_REQ GPDMA_REQ_UART4_RX +#define STM32_UART5_RXDMA_REQ GPDMA_REQ_UART5_RX + +#endif /* __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32_DMASIGMAP_H */
