Swatantra-66 commented on issue #20483:
URL: https://github.com/apache/nuttx/issues/20483#issuecomment-6252294879
Hi @acassis, @xiaoxiang781216,
It has been about 5 days since ccache was enabled in master, and cache
saving, restoration, and eviction have been operating stably across PRs and
master merges with no workflow issues.
Since the observation period went well, I would like to move forward with
**Phase 2 (Chip / Architecture Build Filtering)** so chip-isolated PRs (like
#20477 on i.MX RT) don't trigger builds for all unrelated chip targets.
To avoid both matrix explosion and runtime imbalance (since STM32 alone
represents ~40% of all ARM defconfigs), I propose a **Hybrid Approach**:
1. **Balanced Family Testlists (`tools/ci/testlist/`):**
Replace the arbitrary alphanumeric partitions (`arm-01` to `arm-14`) with
balanced vendor/family groups (~10–12 jobs of roughly equal compile duration):
- `arm-stm32f1-4.dat`
- `arm-stm32f7-h7.dat`
- `arm-stm32l-u-g.dat`
- `arm-imxrt.dat`
- `arm-nrf-rp.dat` (nRF52/53 + RP2040/RP2350)
- `arm-sam.dat` (SAM3/4/D/E/V)
- `arm-nxp.dat` (LPC, Kinetis, S32K)
- `arm-other.dat` (remaining architectures)
2. **Targeted Matrix Routing (`.github/workflows/arch.yml`):**
- If a PR is strictly confined to `arch/arm/src/<chip>/**` and
`boards/arm/<chip>/**` (with no core OS or `arch/arm/src/common` changes), the
workflow only schedules the matching family job (e.g. only `arm-imxrt` runs in
~2–3 minutes instead of launching 14 jobs taking 25+ minutes).
- If core files (`sched/`, `fs/`, `include/`, or `arch/arm/src/common`)
are modified, all family jobs run as usual to guarantee full regression
coverage.
This combines the clean readability and zero-wasted-runner benefits of
family grouping with balanced build times.
If this approach looks good to you, I can proceed.
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