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commit a17dc149842469ad6adc4a977571cf19c6098ae0 Author: Max Kriegleder <[email protected]> AuthorDate: Fri Oct 23 15:29:24 2026 +0200 arch/xtensa/esp32s3: Size the OTG device FIFOs to the hardware. The OTG device driver partitioned 1280 bytes of FIFO RAM, the STM32F4 OTG_FS figure. On the ESP32-S3, GHWCFG3 reports a data FIFO depth of 200 words (800 bytes). With the default layout the IN TxFIFOs started past the end of that RAM and aliased the RxFIFO, so OUT packets from the host overwrote data queued for pending IN transfers. Partition 800 bytes instead. Found with CDC-ACM on an ESP32-S3 board (default three extra endpoints): host commands arriving while the board streamed data corrupted bulk-IN transfers and wedged the link. With the fix the link has run without corruption since. Assisted-by: Claude:claude-opus-5-5 Signed-off-by: Max Kriegleder <[email protected]> --- arch/xtensa/src/esp32s3/esp32s3_otg_device.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/xtensa/src/esp32s3/esp32s3_otg_device.c b/arch/xtensa/src/esp32s3/esp32s3_otg_device.c index e82023f8947..6ffb1725aa4 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_otg_device.c +++ b/arch/xtensa/src/esp32s3/esp32s3_otg_device.c @@ -63,14 +63,18 @@ /* USB hardware definition */ -#define ESP32S3_FIFO_SIZE (1280) +/* GHWCFG3 reports a 200-word data FIFO. Sizing past it places the IN + * TxFIFOs beyond the FIFO RAM, where they alias the RxFIFO. + */ + +#define ESP32S3_FIFO_SIZE (800) #define ESP32S3_FIFO_WORDS (ESP32S3_FIFO_SIZE >> 2) /* EP0 + additional EP */ #define ESP32S3_ENDPOINT_NUM (CONFIG_ESP32S3_OTG_ENDPOINT_NUM + 1) -/* There is 1.25Kb of FIFO memory. The default partitions this memory +/* There are 800 bytes of FIFO memory. The default partitions this memory * so that there is a TxFIFO allocated for each endpoint and with more * memory provided for the common RxFIFO. A more knowledge-able * configuration would not allocate any TxFIFO space to OUT endpoints.
