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commit 0b10aefb58372a418bbfe017838f8e65fd795230 Author: Max Kriegleder <[email protected]> AuthorDate: Fri Oct 23 15:39:02 2026 +0200 arch/xtensa/esp32s3: Set the MSPI clock when flash tuning is off. esp32s3_spi_timing_set_mspi_flash_tuning() programmed the SPI0/SPI1 clocks only at the end of timing tuning, which is compiled in only for DTR or for STR above 80 MHz. Otherwise the function was empty, and SPI0, which fills the instruction cache, kept whatever clock the bootloader left. Simple boot sets it from the app image header, so it matches; with MCUboot it is MCUboot's own flash frequency, and CONFIG_ESP32S3_FLASH_FREQ only reached SPI1. Call esp32s3_spi_timing_set_mspi_high_speed() whether or not tuning ran. It also programmed the PSRAM clock with a divider of 0 when no PSRAM is configured, writing garbage to SPI_MEM_SRAM_CLK_REG; skip that write. Found on an ESP32-S3 board booting through MCUboot built at 40 MHz with the app at 80 MHz: code ran about 1.5x slower than expected, and with the fix it runs at the configured flash frequency. Assisted-by: Claude:claude-opus-5-5 Signed-off-by: Max Kriegleder <[email protected]> --- arch/xtensa/src/esp32s3/esp32s3_spi_timing.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/xtensa/src/esp32s3/esp32s3_spi_timing.c b/arch/xtensa/src/esp32s3/esp32s3_spi_timing.c index 2657064cd08..f2e98860ca8 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_spi_timing.c +++ b/arch/xtensa/src/esp32s3/esp32s3_spi_timing.c @@ -1417,7 +1417,10 @@ void IRAM_ATTR esp32s3_spi_timing_set_mspi_high_speed(bool spi1) set_flash_clock(1, flash_div); } - set_psram_clock(0, psram_div); + if (psram_div != 0) + { + set_psram_clock(0, psram_div); + } #if ESP32S3_SPI_TIMING_FLASH_TUNING || ESP32S3_SPI_TIMING_PSRAM_TUNING set_timing_tuning_regs(true); @@ -1566,6 +1569,11 @@ void IRAM_ATTR esp32s3_spi_timing_set_mspi_flash_tuning(void) sizeof(reference_data)); get_flash_tuning_configs(&timing_configs); do_tuning(reference_data, &timing_configs, true); - esp32s3_spi_timing_set_mspi_high_speed(true); #endif + + /* Without tuning, SPI0 would otherwise keep the clock the bootloader + * left, not CONFIG_ESP32S3_FLASH_FREQ. + */ + + esp32s3_spi_timing_set_mspi_high_speed(true); }
