daniel-p-carvalho opened a new pull request, #20989: URL: https://github.com/apache/nuttx/pull/20989
## Summary The STM32G4 ADC can oversample the regular group in hardware (CFGR2: ROVSE, OVSR, OVSS, TROVS), but the driver never set these bits. Add `STM32_ADCn_OVERSAMPLE`, `STM32_ADCn_OVSR`, `STM32_ADCn_OVSS` and `STM32_ADCn_TROVS`, written when the ADC is configured and still disabled. The options already existed for ADC1 and ADC2 of the STM32H5, which has the same register layout and meaning. They move to a menu shared by the H5 and the G4, which also gets ADC3 to ADC5. The data register is 16 bits wide, so the Kconfig help warns that the sum overflows it silently when OVSS is too small for the ratio. ## Impact - New feature added? YES, optional G4 ADC hardware oversampling, off by default - Existing feature changed? NO (the H5 option names and meaning are kept) - Impact on user (will user need to adapt to change)? NO - Impact on build? YES, the H5 ADC1/ADC2 oversampling options move to another Kconfig menu - Impact on hardware? YES, STM32G4 ADC only, when the option is enabled - Impact on documentation? NO - Impact on security? NO - Impact on compatibility? NO ## Testing Host: Linux x86_64, arm-none-eabi-gcc 15.2.1. Target: custom STM32G474RE board, ADC1 with 8 channels, 64x oversampling (`OVSR=5`, `OVSS=2`): `CFGR2` reads 0x055 and the standard deviation of the channels drops from 0.36-1.5 LSB to 0.06-0.22 LSB. An STM32H5 build with ADC1 and ADC2 oversampling still compiles. `checkpatch.sh -c -u -m -g` passes. Not tested: ADC2 to ADC5 on the G4, `TROVS` and DMA mode. -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
