Sarthak-Pandey opened a new pull request, #20993: URL: https://github.com/apache/nuttx/pull/20993
## Summary Fixes #20969. On STM32 USART v2 and v3 peripheral IPs, the `PCE` (Parity Control Enable), `PS` (Parity Selection), and `M0`/`M1` (Word Length) bits in the `USART_CR1` register can only be written while the USART peripheral is disabled (`UE = 0`). Previously, several STM32 drivers handled `TCSETS` by calling `setformat()` while `UE = 1`. Because the hardware write protection silently ignores CR1 writes when `UE = 1`, `tcsetattr()` returned 0 (success), but the parity and word length did not change (e.g. 8E1 requests silently stayed 8N1). This PR extends the verified pattern implemented for STM32L4 in #20914 (and already used by H7, F7, and G4) to all remaining affected STM32 serial drivers: 1. `arch/arm/src/stm32wb/stm32wb_serial.c` 2. `arch/arm/src/stm32wl5/stm32wl5_serial.c` 3. `arch/arm/src/stm32n6/stm32_serial.c` 4. `arch/arm/src/common/stm32/stm32_serial_m33_v3.c` (STM32L5 / U5 / H5) 5. `arch/arm/src/common/stm32/stm32_serial_m0_v3.c` (STM32F0) 6. `arch/arm/src/common/stm32/stm32_serial_m3m4_v1v2v3v4.c` (STM32F3 branch) ### Changes: - Before clearing `UE`, check if the transmitter is actively enabled (`UE=1 && TE=1`) and wait for the `TC` (Transmission Complete) flag with a timeout. This ensures in-flight characters are not truncated when `UE` transitions to 0, while keeping CPU interrupts unmasked during the drain. - Inside a critical section (`enter_critical_section()`), save `cr1_ue`, clear `UE = 0`, write the format/baud configurations to CR1/CR2/CR3, and restore the original `UE` state (`cr1_ue`). - Extend the F3 branch (`CONFIG_STM32_STM32F30XX / F33XX / F37XX`) in `stm32_serial_m3m4_v1v2v3v4.c` to clear and restore `UE|TE|RE` alongside G4. ## Impact - **Is new feature added?** No. - **User impact:** Fixes silent failure where dynamic parity/word-length reconfiguration via `tcsetattr()` was ignored by hardware. Communication with parity-dependent devices (e.g. Modbus RTU 8E1) now works properly. - **Build impact:** None. - **Hardware impact:** Affects STM32WB, STM32WL5, STM32N6, STM32L5/U5/H5, STM32F0, and STM32F3 peripherals. ## Testing - Verified register sequence logic against STM32 Reference Manuals (RM0394, RM0434, RM0453, RM0091, RM0316). - Checked against established pattern in `arch/arm/src/stm32l4/stm32l4_serial.c` (PR #20914) and `arch/arm/src/stm32h7/stm32_serial.c`. - Verified CR1 read-back behavior ensuring `USART_CR1_PCE` and `USART_CR1_M0` bits latch successfully after `tcsetattr()`. - Static analysis and compilation check across modified architectures. -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
