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commit 3936c2807667c45aa6bc8971b6ad164b74372c17 Author: Royyan Zahir <[email protected]> AuthorDate: Wed Sep 30 18:47:03 2026 +0400 arch, sched: nxstyle in files the uaccess series touches Blank lines after declarations, one declaration per line and case alignment, so the check passes on the files the next commits change. No code changes. Signed-off-by: Royyan Zahir <[email protected]> --- arch/arm64/src/common/arm64_mmu.c | 81 +++++++++++++++++---------------- arch/x86_64/src/common/x86_64_addrenv.c | 1 + 2 files changed, 43 insertions(+), 39 deletions(-) diff --git a/arch/arm64/src/common/arm64_mmu.c b/arch/arm64/src/common/arm64_mmu.c index 626bce9dabf..8792517b2a4 100644 --- a/arch/arm64/src/common/arm64_mmu.c +++ b/arch/arm64/src/common/arm64_mmu.c @@ -358,44 +358,44 @@ static void set_pte_block_desc(uint64_t *pte, uint64_t addr_pa, switch (mem_type) { - case MT_DEVICE_NGNRNE: - case MT_DEVICE_NGNRE: - case MT_DEVICE_GRE: - { - /* Access to Device memory and non-cacheable memory are coherent - * for all observers in the system and are treated as - * Outer shareable, so, for these 2 types of memory, - * it is not strictly needed to set shareability field - */ - - desc |= PTE_BLOCK_DESC_OUTER_SHARE; - - /* Map device memory as execute-never */ - - desc |= PTE_BLOCK_DESC_PXN; - desc |= PTE_BLOCK_DESC_UXN; - break; - } - - case MT_NORMAL_NC: - case MT_NORMAL: - { - /* Make Normal RW memory as execute never */ - - if (attrs & MT_EXECUTE_NEVER) - { - desc |= PTE_BLOCK_DESC_PXN; - } - - if (mem_type == MT_NORMAL) - { - desc |= PTE_BLOCK_DESC_INNER_SHARE; - } - else - { - desc |= PTE_BLOCK_DESC_OUTER_SHARE; - } - } + case MT_DEVICE_NGNRNE: + case MT_DEVICE_NGNRE: + case MT_DEVICE_GRE: + { + /* Access to Device memory and non-cacheable memory are coherent + * for all observers in the system and are treated as + * Outer shareable, so, for these 2 types of memory, + * it is not strictly needed to set shareability field + */ + + desc |= PTE_BLOCK_DESC_OUTER_SHARE; + + /* Map device memory as execute-never */ + + desc |= PTE_BLOCK_DESC_PXN; + desc |= PTE_BLOCK_DESC_UXN; + break; + } + + case MT_NORMAL_NC: + case MT_NORMAL: + { + /* Make Normal RW memory as execute never */ + + if (attrs & MT_EXECUTE_NEVER) + { + desc |= PTE_BLOCK_DESC_PXN; + } + + if (mem_type == MT_NORMAL) + { + desc |= PTE_BLOCK_DESC_INNER_SHARE; + } + else + { + desc |= PTE_BLOCK_DESC_OUTER_SHARE; + } + } } #if defined(CONFIG_MMU_DEBUG) && defined(CONFIG_MMU_DUMP_PTE) @@ -531,7 +531,8 @@ static void init_xlat_tables(const struct arm_mmu_region *region) static void setup_page_tables(void) { - uint64_t max_va = 0, max_pa = 0; + uint64_t max_va = 0; + uint64_t max_pa = 0; const struct arm_mmu_region *region; unsigned int index; @@ -574,6 +575,7 @@ static void setup_page_tables(void) static void enable_mmu_el3(unsigned int flags) { uint64_t value; + UNUSED(flags); /* Set MAIR, TCR and TBBR registers */ @@ -606,6 +608,7 @@ static void enable_mmu_el3(unsigned int flags) static void enable_mmu_el1(unsigned int flags) { uint64_t value; + UNUSED(flags); /* Set MAIR, TCR and TBBR registers */ diff --git a/arch/x86_64/src/common/x86_64_addrenv.c b/arch/x86_64/src/common/x86_64_addrenv.c index 5c2855089a0..933263b0155 100644 --- a/arch/x86_64/src/common/x86_64_addrenv.c +++ b/arch/x86_64/src/common/x86_64_addrenv.c @@ -130,6 +130,7 @@ static void map_spgtables(arch_addrenv_t *addrenv, uintptr_t vaddr) for (i = 0; i < (ARCH_SPGTS - 1); i++) { uintptr_t next = addrenv->spgtables[i + 1]; + mmu_ln_setentry(i, prev, next, vaddr, MMU_UPGT_FLAGS); prev = x86_64_pgvaddr(next); }
