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new 4e8521a60dc arch/arm/stm32h7: Fix stm32h7s3l8 RCC_BMCFGR field name
4e8521a60dc is described below
commit 4e8521a60dc40a29d45a200533f211831007c453
Author: Peter Barada <[email protected]>
AuthorDate: Mon Oct 26 16:36:57 2026 -0400
arch/arm/stm32h7: Fix stm32h7s3l8 RCC_BMCFGR field name
STM32H7S3L8 renamed stm32h7 D1 domain AHB prescaler from HPRE to
BMPRE bus mantrix clock prescaler (which generates AXI peripheral
clock from sys-cpu-ck). See 8.7.8 of ST RM0433 for STM32H7 HPRE
and 7.8.8 of ST RM0477 for STM32H7RSxx BMPRE definitions.
Change field name in stm32h7rsxx_rcc.h and usage in stm32h7rsxx_rcc.c,
as well as nucleo-h7s3l8 and stm32h7s8-dk board.h files.
Signed-off-by Peter Barada <[email protected]>
---
arch/arm/src/stm32h7/hardware/stm32h7rsxx_rcc.h | 21 ++++++++++-----------
arch/arm/src/stm32h7/stm32h7rsxx_rcc.c | 2 +-
boards/arm/stm32h7/nucleo-h7s3l8/include/board.h | 2 +-
boards/arm/stm32h7/stm32h7s8-dk/include/board.h | 2 +-
4 files changed, 13 insertions(+), 14 deletions(-)
diff --git a/arch/arm/src/stm32h7/hardware/stm32h7rsxx_rcc.h
b/arch/arm/src/stm32h7/hardware/stm32h7rsxx_rcc.h
index 7e5726e8469..29340b878b7 100644
--- a/arch/arm/src/stm32h7/hardware/stm32h7rsxx_rcc.h
+++ b/arch/arm/src/stm32h7/hardware/stm32h7rsxx_rcc.h
@@ -256,17 +256,16 @@
# define RCC_CDCFGR_CPRE_SYSCLKd256 (14 << RCC_CDCFGR_CPRE_SHIFT)
# define RCC_CDCFGR_CPRE_SYSCLKd512 (15 << RCC_CDCFGR_CPRE_SHIFT)
-#define RCC_BMCFGR_HPRE_SHIFT (0) /* AHB clock prescaler */
-#define RCC_BMCFGR_HPRE_MASK (15 << RCC_BMCFGR_HPRE_SHIFT)
-# define RCC_BMCFGR_HPRE_SYSCLK (0 << RCC_BMCFGR_HPRE_SHIFT)
-# define RCC_BMCFGR_HPRE_SYSCLKd2 (8 << RCC_BMCFGR_HPRE_SHIFT)
-# define RCC_BMCFGR_HPRE_SYSCLKd4 (9 << RCC_BMCFGR_HPRE_SHIFT)
-# define RCC_BMCFGR_HPRE_SYSCLKd8 (10 << RCC_BMCFGR_HPRE_SHIFT)
-# define RCC_BMCFGR_HPRE_SYSCLKd16 (11 << RCC_BMCFGR_HPRE_SHIFT)
-# define RCC_BMCFGR_HPRE_SYSCLKd64 (12 << RCC_BMCFGR_HPRE_SHIFT)
-# define RCC_BMCFGR_HPRE_SYSCLKd128 (13 << RCC_BMCFGR_HPRE_SHIFT)
-# define RCC_BMCFGR_HPRE_SYSCLKd256 (14 << RCC_BMCFGR_HPRE_SHIFT)
-# define RCC_BMCFGR_HPRE_SYSCLKd512 (15 << RCC_BMCFGR_HPRE_SHIFT)
+#define RCC_BMCFGR_BMPRE_SHIFT (0) /* AHB clock prescaler */
+#define RCC_BMCFGR_BMPRE_MASK (15 << RCC_BMCFGR_BMPRE_SHIFT)
+# define RCC_BMCFGR_BMPRE_SYSCLK (0 << RCC_BMCFGR_BMPRE_SHIFT)
+# define RCC_BMCFGR_BMPRE_SYSCLKd2 (8 << RCC_BMCFGR_BMPRE_SHIFT)
+# define RCC_BMCFGR_BMPRE_SYSCLKd4 (9 << RCC_BMCFGR_BMPRE_SHIFT)
+# define RCC_BMCFGR_BMPRE_SYSCLKd8 (10 << RCC_BMCFGR_BMPRE_SHIFT)
+# define RCC_BMCFGR_BMPRE_SYSCLKd16 (11 << RCC_BMCFGR_BMPRE_SHIFT)
+# define RCC_BMCFGR_BMPRE_SYSCLKd64 (12 << RCC_BMCFGR_BMPRE_SHIFT)
+# define RCC_BMCFGR_BMPRE_SYSCLKd128 (13 << RCC_BMCFGR_BMPRE_SHIFT)
+# define RCC_BMCFGR_BMPRE_SYSCLKd256 (14 << RCC_BMCFGR_BMPRE_SHIFT)#
define RCC_BMCFGR_BMPRE_SYSCLKd512 (15 << RCC_BMCFGR_BMPRE_SHIFT)
#define RCC_APBCFGR_PPRE1_SHIFT (0) /* APB1 clock prescaler */
#define RCC_APBCFGR_PPRE1_MASK (7 << RCC_APBCFGR_PPRE1_SHIFT)
diff --git a/arch/arm/src/stm32h7/stm32h7rsxx_rcc.c
b/arch/arm/src/stm32h7/stm32h7rsxx_rcc.c
index 10a4299a3d8..9df6e4dbb28 100644
--- a/arch/arm/src/stm32h7/stm32h7rsxx_rcc.c
+++ b/arch/arm/src/stm32h7/stm32h7rsxx_rcc.c
@@ -571,7 +571,7 @@ void stm32_stdclockconfig(void)
/* Configure the CPU, bus matrix and APB prescalers */
putreg32(STM32_RCC_CDCFGR_CPRE, STM32_RCC_CDCFGR);
- putreg32(STM32_RCC_BMCFGR_HPRE, STM32_RCC_BMCFGR);
+ putreg32(STM32_RCC_BMCFGR_BMPRE, STM32_RCC_BMCFGR);
putreg32(STM32_RCC_APBCFGR_PPRE1 | STM32_RCC_APBCFGR_PPRE2 |
STM32_RCC_APBCFGR_PPRE4 | STM32_RCC_APBCFGR_PPRE5,
STM32_RCC_APBCFGR);
diff --git a/boards/arm/stm32h7/nucleo-h7s3l8/include/board.h
b/boards/arm/stm32h7/nucleo-h7s3l8/include/board.h
index f5c52b315c1..4330eb33f22 100644
--- a/boards/arm/stm32h7/nucleo-h7s3l8/include/board.h
+++ b/boards/arm/stm32h7/nucleo-h7s3l8/include/board.h
@@ -110,7 +110,7 @@
/* AHB clock (HCLK) is SYSCLK/2 (300 MHz). */
-#define STM32_RCC_BMCFGR_HPRE RCC_BMCFGR_HPRE_SYSCLKd2
+#define STM32_RCC_BMCFGR_BMPRE RCC_BMCFGR_BMPRE_SYSCLKd2
#define STM32_HCLK_FREQUENCY (STM32_SYSCLK_FREQUENCY / 2)
/* APB1, APB2, APB4 and APB5 clocks are HCLK/2 (150 MHz). */
diff --git a/boards/arm/stm32h7/stm32h7s8-dk/include/board.h
b/boards/arm/stm32h7/stm32h7s8-dk/include/board.h
index 1b475219c47..d5dac67356e 100644
--- a/boards/arm/stm32h7/stm32h7s8-dk/include/board.h
+++ b/boards/arm/stm32h7/stm32h7s8-dk/include/board.h
@@ -110,7 +110,7 @@
/* AHB clock (HCLK) is SYSCLK/2 (300 MHz). */
-#define STM32_RCC_BMCFGR_HPRE RCC_BMCFGR_HPRE_SYSCLKd2
+#define STM32_RCC_BMCFGR_BMPRE RCC_BMCFGR_BMPRE_SYSCLKd2
#define STM32_HCLK_FREQUENCY (STM32_SYSCLK_FREQUENCY / 2)
/* APB1, APB2, APB4 and APB5 clocks are HCLK/2 (150 MHz). */
