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commit 366b2c69346ad64bf2bd7b2b36fd349bc57419ab Author: Max Kriegleder <[email protected]> AuthorDate: Tue Oct 27 00:55:42 2026 +0100 arch/arm/stm32h7: Fix nxstyle errors in stm32_serial.c. Fix the coding standard violations nxstyle reports in the whole file, so that checkpatch passes on the next commit: * Indent the case labels and their code inside every switch. * Add the missing blank lines after local variable declarations. * Fix four statements and the start of stm32_serial_dma_poll() that were indented by an odd number or too far. No functional change: the object code is identical (nucleo-h753zi:nsh with USART6, PM, and with and without USART6 RX/TX DMA). Assisted-by: Claude:claude-opus-5-5 Signed-off-by: Max Kriegleder <[email protected]> --- arch/arm/src/stm32h7/stm32_serial.c | 654 ++++++++++++++++++------------------ 1 file changed, 330 insertions(+), 324 deletions(-) diff --git a/arch/arm/src/stm32h7/stm32_serial.c b/arch/arm/src/stm32h7/stm32_serial.c index d4f039244bc..ed233257427 100644 --- a/arch/arm/src/stm32h7/stm32_serial.c +++ b/arch/arm/src/stm32h7/stm32_serial.c @@ -1988,55 +1988,55 @@ static void up_set_apb_clock(struct uart_dev_s *dev, bool on) switch (priv->usartbase) { - default: - return; + default: + return; #ifdef CONFIG_STM32_USART1 - case STM32_USART1_BASE: - rcc_en = RCC_APB2ENR_USART1EN; - regaddr = STM32_RCC_APB2ENR; - break; + case STM32_USART1_BASE: + rcc_en = RCC_APB2ENR_USART1EN; + regaddr = STM32_RCC_APB2ENR; + break; #endif #ifdef CONFIG_STM32_USART2 - case STM32_USART2_BASE: - rcc_en = RCC_APB1LENR_USART2EN; - regaddr = STM32_RCC_APB1LENR; - break; + case STM32_USART2_BASE: + rcc_en = RCC_APB1LENR_USART2EN; + regaddr = STM32_RCC_APB1LENR; + break; #endif #ifdef CONFIG_STM32_USART3 - case STM32_USART3_BASE: - rcc_en = RCC_APB1LENR_USART3EN; - regaddr = STM32_RCC_APB1LENR; - break; + case STM32_USART3_BASE: + rcc_en = RCC_APB1LENR_USART3EN; + regaddr = STM32_RCC_APB1LENR; + break; #endif #ifdef CONFIG_STM32_UART4 - case STM32_UART4_BASE: - rcc_en = RCC_APB1LENR_UART4EN; - regaddr = STM32_RCC_APB1LENR; - break; + case STM32_UART4_BASE: + rcc_en = RCC_APB1LENR_UART4EN; + regaddr = STM32_RCC_APB1LENR; + break; #endif #ifdef CONFIG_STM32_UART5 - case STM32_UART5_BASE: - rcc_en = RCC_APB1LENR_UART5EN; - regaddr = STM32_RCC_APB1LENR; - break; + case STM32_UART5_BASE: + rcc_en = RCC_APB1LENR_UART5EN; + regaddr = STM32_RCC_APB1LENR; + break; #endif #ifdef CONFIG_STM32_USART6 - case STM32_USART6_BASE: - rcc_en = RCC_APB2ENR_USART6EN; - regaddr = STM32_RCC_APB2ENR; - break; + case STM32_USART6_BASE: + rcc_en = RCC_APB2ENR_USART6EN; + regaddr = STM32_RCC_APB2ENR; + break; #endif #ifdef CONFIG_STM32_UART7 - case STM32_UART7_BASE: - rcc_en = RCC_APB1LENR_UART7EN; - regaddr = STM32_RCC_APB1LENR; - break; + case STM32_UART7_BASE: + rcc_en = RCC_APB1LENR_UART7EN; + regaddr = STM32_RCC_APB1LENR; + break; #endif #ifdef CONFIG_STM32_UART8 - case STM32_UART8_BASE: - rcc_en = RCC_APB1LENR_UART8EN; - regaddr = STM32_RCC_APB1LENR; - break; + case STM32_UART8_BASE: + rcc_en = RCC_APB1LENR_UART8EN; + regaddr = STM32_RCC_APB1LENR; + break; #endif } @@ -2434,7 +2434,7 @@ static int up_attach(struct uart_dev_s *dev) * in the USART */ - up_enable_irq(priv->irq); + up_enable_irq(priv->irq); } return ret; @@ -2453,6 +2453,7 @@ static int up_attach(struct uart_dev_s *dev) static void up_detach(struct uart_dev_s *dev) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + up_disable_irq(priv->irq); irq_detach(priv->irq); } @@ -2603,346 +2604,349 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) switch (cmd) { #ifdef CONFIG_SERIAL_TIOCSERGSTRUCT - case TIOCSERGSTRUCT: - { - struct up_dev_s *user = (struct up_dev_s *)arg; - if (!user) - { - ret = -EINVAL; - } - else - { - memcpy(user, dev, sizeof(struct up_dev_s)); - } - } - break; + case TIOCSERGSTRUCT: + { + struct up_dev_s *user = (struct up_dev_s *)arg; + + if (!user) + { + ret = -EINVAL; + } + else + { + memcpy(user, dev, sizeof(struct up_dev_s)); + } + } + break; #endif #ifdef CONFIG_STM32_USART_SINGLEWIRE - case TIOCSSINGLEWIRE: - { - uint32_t cr1; - uint32_t cr1_ue; - irqstate_t flags; - - flags = enter_critical_section(); - - /* Get the original state of UE */ + case TIOCSSINGLEWIRE: + { + uint32_t cr1; + uint32_t cr1_ue; + irqstate_t flags; - cr1 = up_serialin(priv, STM32_USART_CR1_OFFSET); - cr1_ue = cr1 & USART_CR1_UE; - cr1 &= ~USART_CR1_UE; + flags = enter_critical_section(); - /* Disable UE, HDSEL can only be written when UE=0 */ + /* Get the original state of UE */ - up_serialout(priv, STM32_USART_CR1_OFFSET, cr1); + cr1 = up_serialin(priv, STM32_USART_CR1_OFFSET); + cr1_ue = cr1 & USART_CR1_UE; + cr1 &= ~USART_CR1_UE; - /* Change the TX port to be open-drain/push-pull and enable/disable - * half-duplex mode. - */ + /* Disable UE, HDSEL can only be written when UE=0 */ - uint32_t cr = up_serialin(priv, STM32_USART_CR3_OFFSET); + up_serialout(priv, STM32_USART_CR1_OFFSET, cr1); - if ((arg & SER_SINGLEWIRE_ENABLED) != 0) - { - uint32_t gpio_val = (arg & SER_SINGLEWIRE_PUSHPULL) == - SER_SINGLEWIRE_PUSHPULL ? - GPIO_PUSHPULL : GPIO_OPENDRAIN; - gpio_val |= (arg & SER_SINGLEWIRE_PULL_MASK) == - SER_SINGLEWIRE_PULLUP ? - GPIO_PULLUP : GPIO_FLOAT; - gpio_val |= (arg & SER_SINGLEWIRE_PULL_MASK) == - SER_SINGLEWIRE_PULLDOWN ? - GPIO_PULLDOWN : GPIO_FLOAT; - if (priv->tx_gpio != 0) - { - stm32_configgpio((priv->tx_gpio & - ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | - gpio_val); - } + /* Change the TX port to be open-drain/push-pull and enable/disable + * half-duplex mode. + */ - cr |= USART_CR3_HDSEL; - } - else - { - if (priv->tx_gpio != 0) - { - stm32_configgpio((priv->tx_gpio & - ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | - GPIO_PUSHPULL); - } + uint32_t cr = up_serialin(priv, STM32_USART_CR3_OFFSET); - cr &= ~USART_CR3_HDSEL; - } + if ((arg & SER_SINGLEWIRE_ENABLED) != 0) + { + uint32_t gpio_val = (arg & SER_SINGLEWIRE_PUSHPULL) == + SER_SINGLEWIRE_PUSHPULL ? + GPIO_PUSHPULL : GPIO_OPENDRAIN; + + gpio_val |= (arg & SER_SINGLEWIRE_PULL_MASK) == + SER_SINGLEWIRE_PULLUP ? + GPIO_PULLUP : GPIO_FLOAT; + gpio_val |= (arg & SER_SINGLEWIRE_PULL_MASK) == + SER_SINGLEWIRE_PULLDOWN ? + GPIO_PULLDOWN : GPIO_FLOAT; + if (priv->tx_gpio != 0) + { + stm32_configgpio((priv->tx_gpio & + ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | + gpio_val); + } + + cr |= USART_CR3_HDSEL; + } + else + { + if (priv->tx_gpio != 0) + { + stm32_configgpio((priv->tx_gpio & + ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | + GPIO_PUSHPULL); + } + + cr &= ~USART_CR3_HDSEL; + } - up_serialout(priv, STM32_USART_CR3_OFFSET, cr); + up_serialout(priv, STM32_USART_CR3_OFFSET, cr); - /* Re-enable UE if appropriate */ + /* Re-enable UE if appropriate */ - up_serialout(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); - leave_critical_section(flags); - } - break; + up_serialout(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); + leave_critical_section(flags); + } + break; #endif #ifdef CONFIG_STM32_USART_INVERT - case TIOCSINVERT: - { - uint32_t cr1; - uint32_t cr1_ue; - irqstate_t flags; + case TIOCSINVERT: + { + uint32_t cr1; + uint32_t cr1_ue; + irqstate_t flags; - flags = enter_critical_section(); + flags = enter_critical_section(); - /* Get the original state of UE */ + /* Get the original state of UE */ - cr1 = up_serialin(priv, STM32_USART_CR1_OFFSET); - cr1_ue = cr1 & USART_CR1_UE; - cr1 &= ~USART_CR1_UE; + cr1 = up_serialin(priv, STM32_USART_CR1_OFFSET); + cr1_ue = cr1 & USART_CR1_UE; + cr1 &= ~USART_CR1_UE; - /* Disable UE, {R,T}XINV can only be written when UE=0 */ + /* Disable UE, {R,T}XINV can only be written when UE=0 */ - up_serialout(priv, STM32_USART_CR1_OFFSET, cr1); + up_serialout(priv, STM32_USART_CR1_OFFSET, cr1); - /* Enable/disable signal inversion. */ + /* Enable/disable signal inversion. */ - uint32_t cr = up_serialin(priv, STM32_USART_CR2_OFFSET); + uint32_t cr = up_serialin(priv, STM32_USART_CR2_OFFSET); - if (arg & SER_INVERT_ENABLED_RX) - { - cr |= USART_CR2_RXINV; - } - else - { - cr &= ~USART_CR2_RXINV; - } + if (arg & SER_INVERT_ENABLED_RX) + { + cr |= USART_CR2_RXINV; + } + else + { + cr &= ~USART_CR2_RXINV; + } - if (arg & SER_INVERT_ENABLED_TX) - { - cr |= USART_CR2_TXINV; - } - else - { - cr &= ~USART_CR2_TXINV; - } + if (arg & SER_INVERT_ENABLED_TX) + { + cr |= USART_CR2_TXINV; + } + else + { + cr &= ~USART_CR2_TXINV; + } - up_serialout(priv, STM32_USART_CR2_OFFSET, cr); + up_serialout(priv, STM32_USART_CR2_OFFSET, cr); - /* Re-enable UE if appropriate */ + /* Re-enable UE if appropriate */ - up_serialout(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); - leave_critical_section(flags); - } - break; + up_serialout(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); + leave_critical_section(flags); + } + break; #endif #ifdef CONFIG_STM32_USART_SWAP - case TIOCSSWAP: - { - uint32_t cr1; - uint32_t cr1_ue; - irqstate_t flags; + case TIOCSSWAP: + { + uint32_t cr1; + uint32_t cr1_ue; + irqstate_t flags; - flags = enter_critical_section(); + flags = enter_critical_section(); - /* Get the original state of UE */ + /* Get the original state of UE */ - cr1 = up_serialin(priv, STM32_USART_CR1_OFFSET); - cr1_ue = cr1 & USART_CR1_UE; - cr1 &= ~USART_CR1_UE; + cr1 = up_serialin(priv, STM32_USART_CR1_OFFSET); + cr1_ue = cr1 & USART_CR1_UE; + cr1 &= ~USART_CR1_UE; - /* Disable UE, SWAP can only be written when UE=0 */ + /* Disable UE, SWAP can only be written when UE=0 */ - up_serialout(priv, STM32_USART_CR1_OFFSET, cr1); + up_serialout(priv, STM32_USART_CR1_OFFSET, cr1); - /* Enable/disable Swap mode. */ + /* Enable/disable Swap mode. */ - uint32_t cr = up_serialin(priv, STM32_USART_CR2_OFFSET); + uint32_t cr = up_serialin(priv, STM32_USART_CR2_OFFSET); - if (arg == SER_SWAP_ENABLED) - { - cr |= USART_CR2_SWAP; - } - else - { - cr &= ~USART_CR2_SWAP; - } + if (arg == SER_SWAP_ENABLED) + { + cr |= USART_CR2_SWAP; + } + else + { + cr &= ~USART_CR2_SWAP; + } - up_serialout(priv, STM32_USART_CR2_OFFSET, cr); + up_serialout(priv, STM32_USART_CR2_OFFSET, cr); - /* Re-enable UE if appropriate */ + /* Re-enable UE if appropriate */ - up_serialout(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); - leave_critical_section(flags); - } - break; + up_serialout(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); + leave_critical_section(flags); + } + break; #endif #ifdef CONFIG_SERIAL_TERMIOS - case TCGETS: - { - struct termios *termiosp = (struct termios *)arg; + case TCGETS: + { + struct termios *termiosp = (struct termios *)arg; - if (!termiosp) - { - ret = -EINVAL; - break; - } + if (!termiosp) + { + ret = -EINVAL; + break; + } - /* Note that since we only support 8/9 bit modes and - * there is no way to report 9-bit mode, we always claim 8. - */ + /* Note that since we only support 8/9 bit modes and + * there is no way to report 9-bit mode, we always claim 8. + */ - termiosp->c_cflag = - ((priv->parity != 0) ? PARENB : 0) | - ((priv->parity == 1) ? PARODD : 0) | - ((priv->stopbits2) ? CSTOPB : 0) | + termiosp->c_cflag = + ((priv->parity != 0) ? PARENB : 0) | + ((priv->parity == 1) ? PARODD : 0) | + ((priv->stopbits2) ? CSTOPB : 0) | #ifdef CONFIG_SERIAL_OFLOWCONTROL - ((priv->oflow) ? CCTS_OFLOW : 0) | + ((priv->oflow) ? CCTS_OFLOW : 0) | #endif #ifdef CONFIG_SERIAL_IFLOWCONTROL - ((priv->iflow) ? CRTS_IFLOW : 0) | + ((priv->iflow) ? CRTS_IFLOW : 0) | #endif - CS8; + CS8; - cfsetispeed(termiosp, priv->baud); + cfsetispeed(termiosp, priv->baud); - /* TODO: CRTS_IFLOW, CCTS_OFLOW */ - } - break; + /* TODO: CRTS_IFLOW, CCTS_OFLOW */ + } + break; - case TCSETS: - { - struct termios *termiosp = (struct termios *)arg; + case TCSETS: + { + struct termios *termiosp = (struct termios *)arg; - if (!termiosp) - { - ret = -EINVAL; - break; - } + if (!termiosp) + { + ret = -EINVAL; + break; + } - /* Perform some sanity checks before accepting any changes */ + /* Perform some sanity checks before accepting any changes */ - if (((termiosp->c_cflag & CSIZE) != CS8) + if (((termiosp->c_cflag & CSIZE) != CS8) #ifdef CONFIG_SERIAL_OFLOWCONTROL - || ((termiosp->c_cflag & CCTS_OFLOW) && (priv->cts_gpio == 0)) + || ((termiosp->c_cflag & CCTS_OFLOW) && (priv->cts_gpio == 0)) #endif #ifdef CONFIG_SERIAL_IFLOWCONTROL - || ((termiosp->c_cflag & CRTS_IFLOW) && (priv->rts_gpio == 0)) + || ((termiosp->c_cflag & CRTS_IFLOW) && (priv->rts_gpio == 0)) #endif - ) - { - ret = -EINVAL; - break; - } + ) + { + ret = -EINVAL; + break; + } - if (termiosp->c_cflag & PARENB) - { - priv->parity = (termiosp->c_cflag & PARODD) ? 1 : 2; - } - else - { - priv->parity = 0; - } + if (termiosp->c_cflag & PARENB) + { + priv->parity = (termiosp->c_cflag & PARODD) ? 1 : 2; + } + else + { + priv->parity = 0; + } - priv->stopbits2 = (termiosp->c_cflag & CSTOPB) != 0; + priv->stopbits2 = (termiosp->c_cflag & CSTOPB) != 0; #ifdef CONFIG_SERIAL_OFLOWCONTROL - priv->oflow = (termiosp->c_cflag & CCTS_OFLOW) != 0; + priv->oflow = (termiosp->c_cflag & CCTS_OFLOW) != 0; #endif #ifdef CONFIG_SERIAL_IFLOWCONTROL - priv->iflow = (termiosp->c_cflag & CRTS_IFLOW) != 0; + priv->iflow = (termiosp->c_cflag & CRTS_IFLOW) != 0; #endif - /* Note that since there is no way to request 9-bit mode - * and no way to support 5/6/7-bit modes, we ignore them - * all here. - */ + /* Note that since there is no way to request 9-bit mode + * and no way to support 5/6/7-bit modes, we ignore them + * all here. + */ - /* Note that only cfgetispeed is used because we have knowledge - * that only one speed is supported. - */ + /* Note that only cfgetispeed is used because we have knowledge + * that only one speed is supported. + */ - priv->baud = cfgetispeed(termiosp); + priv->baud = cfgetispeed(termiosp); - /* Effect the changes immediately - note that we do not implement - * TCSADRAIN / TCSAFLUSH - */ + /* Effect the changes immediately - note that we do not implement + * TCSADRAIN / TCSAFLUSH + */ - up_set_format(dev); - } - break; + up_set_format(dev); + } + break; #endif /* CONFIG_SERIAL_TERMIOS */ #ifdef CONFIG_STM32_USART_BREAKS # ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT - case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ - { - irqstate_t flags; + case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ + { + irqstate_t flags; - flags = enter_critical_section(); + flags = enter_critical_section(); - /* Disable any further tx activity */ + /* Disable any further tx activity */ - priv->ie |= USART_CR1_IE_BREAK_INPROGRESS; + priv->ie |= USART_CR1_IE_BREAK_INPROGRESS; - up_txint(dev, false); + up_txint(dev, false); - /* Configure TX as a GPIO output pin and Send a break signal */ + /* Configure TX as a GPIO output pin and Send a break signal */ - if (priv->tx_gpio != 0) - { - uint32_t tx_break = GPIO_OUTPUT | - (~(GPIO_MODE_MASK | GPIO_OUTPUT_SET) & priv->tx_gpio); - stm32_configgpio(tx_break); - } + if (priv->tx_gpio != 0) + { + uint32_t tx_break = GPIO_OUTPUT | + (~(GPIO_MODE_MASK | GPIO_OUTPUT_SET) & priv->tx_gpio); - leave_critical_section(flags); - } - break; + stm32_configgpio(tx_break); + } - case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */ - { - irqstate_t flags; + leave_critical_section(flags); + } + break; - flags = enter_critical_section(); + case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */ + { + irqstate_t flags; - /* Configure TX back to U(S)ART */ + flags = enter_critical_section(); - if (priv->tx_gpio != 0) - { - stm32_configgpio(priv->tx_gpio); - } + /* Configure TX back to U(S)ART */ + + if (priv->tx_gpio != 0) + { + stm32_configgpio(priv->tx_gpio); + } - priv->ie &= ~USART_CR1_IE_BREAK_INPROGRESS; + priv->ie &= ~USART_CR1_IE_BREAK_INPROGRESS; - /* Enable further tx activity */ + /* Enable further tx activity */ - up_txint(dev, true); + up_txint(dev, true); - leave_critical_section(flags); - } - break; + leave_critical_section(flags); + } + break; # else - case TIOCSBRK: /* No BSD compatibility: Turn break on for M bit times */ - { - uint32_t cr1; - irqstate_t flags; - - flags = enter_critical_section(); - cr1 = up_serialin(priv, STM32_USART_CR1_OFFSET); - up_serialout(priv, STM32_USART_RQR_OFFSET, cr1 | USART_RQR_SBKRQ); - leave_critical_section(flags); - } - break; - - case TIOCCBRK: /* No BSD compatibility: HW does not support stopping a break */ - break; + case TIOCSBRK: /* No BSD compatibility: Turn break on for M bit times */ + { + uint32_t cr1; + irqstate_t flags; + + flags = enter_critical_section(); + cr1 = up_serialin(priv, STM32_USART_CR1_OFFSET); + up_serialout(priv, STM32_USART_RQR_OFFSET, cr1 | USART_RQR_SBKRQ); + leave_critical_section(flags); + } + break; + + case TIOCCBRK: /* No BSD compatibility: HW does not support stopping a break */ + break; # endif #endif - default: - ret = -ENOTTY; - break; + default: + ret = -ENOTTY; + break; } return ret; @@ -3050,6 +3054,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable) static bool up_rxavailable(struct uart_dev_s *dev) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + return ((up_serialin(priv, STM32_USART_ISR_OFFSET) & USART_ISR_RXNE) != 0); } #endif @@ -3593,6 +3598,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable) static bool up_txready(struct uart_dev_s *dev) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + return ((up_serialin(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TXE) != 0); } @@ -3738,69 +3744,69 @@ static int up_pm_prepare(struct pm_callback_s *cb, int domain, switch (pmstate) { - case PM_NORMAL: - case PM_IDLE: - break; + case PM_NORMAL: + case PM_IDLE: + break; - case PM_STANDBY: - case PM_SLEEP: + case PM_STANDBY: + case PM_SLEEP: #ifdef SERIAL_HAVE_RXDMA - /* Flush Rx DMA buffers before checking state of serial device - * buffers. - */ + /* Flush Rx DMA buffers before checking state of serial device + * buffers. + */ - stm32_serial_dma_poll(); + stm32_serial_dma_poll(); #endif - /* Check if any of the active ports have data pending on Tx/Rx - * buffers. - */ + /* Check if any of the active ports have data pending on Tx/Rx + * buffers. + */ - for (n = 0; n < STM32_NUSART + STM32_NUART; n++) - { - struct up_dev_s *priv = g_uart_devs[n]; + for (n = 0; n < STM32_NUSART + STM32_NUART; n++) + { + struct up_dev_s *priv = g_uart_devs[n]; - if (!priv || !priv->initialized) - { - /* Not active, skip. */ + if (!priv || !priv->initialized) + { + /* Not active, skip. */ - continue; - } + continue; + } - if (priv->suspended) - { - /* Port already suspended, skip. */ + if (priv->suspended) + { + /* Port already suspended, skip. */ - continue; - } + continue; + } - if (priv->dev.isconsole) - { - /* Allow losing some debug traces. */ + if (priv->dev.isconsole) + { + /* Allow losing some debug traces. */ - continue; - } + continue; + } - /* Check if port has data pending (Rx & Tx). */ + /* Check if port has data pending (Rx & Tx). */ - if (priv->dev.xmit.head != priv->dev.xmit.tail) - { - return ERROR; - } + if (priv->dev.xmit.head != priv->dev.xmit.tail) + { + return ERROR; + } - if (priv->dev.recv.head != priv->dev.recv.tail) - { - return ERROR; - } - } - break; + if (priv->dev.recv.head != priv->dev.recv.tail) + { + return ERROR; + } + } + break; - default: + default: - /* Should not get here */ + /* Should not get here */ - break; + break; } return OK; @@ -3967,9 +3973,9 @@ void arm_serialinit(void) #ifdef SERIAL_HAVE_RXDMA void stm32_serial_dma_poll(void) { - irqstate_t flags; + irqstate_t flags; - flags = enter_critical_section(); + flags = enter_critical_section(); #ifdef CONFIG_USART1_RXDMA if (g_usart1priv.rxdma != NULL)
