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commit a96f758d9436b9b6005faf53bc0b2eb1ad13cdf3 Author: Denis V. Meltsaykin <[email protected]> AuthorDate: Wed Oct 28 19:43:45 2026 +0100 arch/rp23xx: Use the armv8-m MPU attribute layout for the shared SRAM. The shared SRAM region set index 0 of MAIR0 to Normal Non-cacheable, while mpu_control() in armv8-m/arm_mpu.c keeps Strongly-ordered there and Non-cacheable at index 2. Should the generic MPU code ever run on rp23xx, it would rewrite MAIR0 and turn the SRAM into Strongly-ordered memory. Program MAIR0 and MAIR1 as mpu_control() does and use MPU_RLAR_NONCACHEABLE. Document that the SRAM takes region 0 and that a resume from suspend to RAM does not set the region up. Also correct the end of the SRAM in the memory map comment: its 520KB ends at 0x20081fff. Signed-off-by: Denis Meltsaykin <[email protected]> Assisted-By: Claude Opus 5.5 <[email protected]> --- arch/arm/src/rp23xx/hardware/rp23xx_memorymap.h | 2 +- arch/arm/src/rp23xx/rp23xx_mpu.h | 18 +++++++++++++++--- 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/arch/arm/src/rp23xx/hardware/rp23xx_memorymap.h b/arch/arm/src/rp23xx/hardware/rp23xx_memorymap.h index 1133c213a49..47233aa9c9e 100644 --- a/arch/arm/src/rp23xx/hardware/rp23xx_memorymap.h +++ b/arch/arm/src/rp23xx/hardware/rp23xx_memorymap.h @@ -46,7 +46,7 @@ ****************************************************************************/ #define RP23XX_FLASH_BASE 0x10000000 /* -0x001fffff: FLASH memory space (2048KB) */ -#define RP23XX_SRAM_BASE 0x20000000 /* -0x20041fff: SRAM memory space (520KB) */ +#define RP23XX_SRAM_BASE 0x20000000 /* -0x20081fff: SRAM memory space (520KB) */ #define RP23XX_SYSINFO_BASE 0x40000000 #define RP23XX_SYSCFG_BASE 0x40008000 /* Register block for various chip control signals */ diff --git a/arch/arm/src/rp23xx/rp23xx_mpu.h b/arch/arm/src/rp23xx/rp23xx_mpu.h index 70c2172600c..1533be38ccf 100644 --- a/arch/arm/src/rp23xx/rp23xx_mpu.h +++ b/arch/arm/src/rp23xx/rp23xx_mpu.h @@ -63,6 +63,13 @@ * is banked per core, so each core must call this before it relies on an * atomic operation. * + * The memory attributes follow the layout of mpu_control() in + * armv8-m/arm_mpu.c, and the SRAM takes MPU region 0, so that region + * must stay reserved should arm_mpu.c ever allocate regions here. + * + * A resume from suspend to RAM does not run this; the suspend support + * does not handle SMP yet, but must call it once it does. + * ****************************************************************************/ static inline void rp23xx_mpu_share_sram(void) @@ -73,14 +80,19 @@ static inline void rp23xx_mpu_share_sram(void) putreg32(0, MPU_CTRL); UP_MB(); - /* Attribute index 0: Normal memory, Non-cacheable */ + /* The same attribute layout as mpu_control() */ - modifyreg32(MPU_MAIR0, 0xff, MPU_MAIR_NONCACHEABLE); + putreg32((MPU_MAIR_STRONGLY_ORDER << 0) | + (MPU_MAIR_DEVICE << 8) | + (MPU_MAIR_NONCACHEABLE << 16) | + (MPU_MAIR_WRITE_THROUGH << 24), + MPU_MAIR0); + putreg32((MPU_MAIR_WRITE_BACK << 0), MPU_MAIR1); putreg32(0, MPU_RNR); putreg32((base & MPU_RBAR_BASE_MASK) | MPU_RBAR_SH_OUTER | MPU_RBAR_AP_RWRW, MPU_RBAR); - putreg32((limit & MPU_RLAR_LIMIT_MASK) | (0 << MPU_RLAR_INDX_SHIFT) | + putreg32((limit & MPU_RLAR_LIMIT_MASK) | MPU_RLAR_NONCACHEABLE | MPU_RLAR_ENABLE, MPU_RLAR); putreg32(MPU_CTRL_ENABLE | MPU_CTRL_PRIVDEFENA, MPU_CTRL);
