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commit 0ba98a951f9c6be73f27f849e853e3d347858bf5 Author: Kerogit <[email protected]> AuthorDate: Mon Mar 9 10:23:50 2026 +0100 arch/avr/src/avrdx/avrdx_gpio_isr_mux: clear flags after handlers run Unlike the edge triggered interrupts, the interrupt flag is raised continuously as long as the pin stays low for level-triggered interrupts. The interrupt flags therefore need to be cleared after the handlers run (presumably, some handler will reset the pin that triggered the interrupt back to high state.) Signed-off-by: Kerogit <[email protected]> --- arch/avr/src/avrdx/avrdx_gpio_isr_mux.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/avr/src/avrdx/avrdx_gpio_isr_mux.c b/arch/avr/src/avrdx/avrdx_gpio_isr_mux.c index 0524bc00925..b166f970077 100644 --- a/arch/avr/src/avrdx/avrdx_gpio_isr_mux.c +++ b/arch/avr/src/avrdx/avrdx_gpio_isr_mux.c @@ -157,10 +157,17 @@ static int avrdx_gpio_isr_mux(int irq, void *context, FAR void *arg) PANIC(); /* IRQ is attached when this is allocated */ } - /* Read pins which triggred the interrupt and clear their flags */ + /* Read pins which triggered the interrupt. Do not clear their flags yet, + * level sense interrupt would trigger again right away (handler will + * presumably prevent that and then we clear the flags.) + * + * Unfortunately, this makes it possible to lose edge-triggered interrupts + * that came in quick succession on the same pin. That's an acceptable + * tradeoff though - level-triggered interrupts need to be supported + * as well. + */ flags = AVRDX_PORT(port_index).INTFLAGS; - AVRDX_PORT(port_index).INTFLAGS = flags; for (i = 0; i < GPIO_MUX_MAX_CHANNELS; i++, port_isrs++) { @@ -170,6 +177,10 @@ static int avrdx_gpio_isr_mux(int irq, void *context, FAR void *arg) } } + /* Clear the flags now when everything was handled. */ + + AVRDX_PORT(port_index).INTFLAGS = flags; + return OK; }
