casaroli commented on code in PR #21308:
URL: https://github.com/apache/nuttx/pull/21308#discussion_r4470503244
##########
arch/tricore/src/common/tricore_doirq.c:
##########
@@ -41,44 +41,113 @@
#include "tricore_internal.h"
+#include "IfxCpu.h"
+#include "IfxInt_reg.h"
+
/****************************************************************************
- * Public Functions
+ * Pre-processor Definitions
****************************************************************************/
-IFX_INTERRUPT_INTERNAL(tricore_doirq, 0, 255)
+#define TRICORE_INT_LASR0_ADDR ((uintptr_t)&INT_LASR0)
+#define TRICORE_INT_LASR_SPACING ((uintptr_t)&INT_LASR1 - \
+ (uintptr_t)&INT_LASR0)
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: tricore_irq_from_lasr
+ *
+ * Description:
+ * Get irq number from ICU's last acknowledged SRN register
+ *
+ ****************************************************************************/
+
+static inline_function int tricore_irq_from_lasr(void)
+{
+ uintptr_t addr = TRICORE_INT_LASR0_ADDR +
+ up_cpu_index() * TRICORE_INT_LASR_SPACING;
+
+ return (getreg32(addr) >> 16) & 0x7ff;
+}
+
+#ifdef CONFIG_ARCH_IRQPRIO
+
+/****************************************************************************
+ * Name: tricore_irq_direct
+ *
+ * Description:
+ * Fast interrupt path (analogous to ARM-M exception_direct).
+ * Only dispatches the IRQ handler, no context switch.
+ * If a context switch is needed, triggers the scheduling GPSR which
+ * will execute after all higher-priority interrupts have returned.
+ *
+ ****************************************************************************/
+
+static void tricore_irq_direct(uintptr_t *regs)
Review Comment:
With `CONFIG_ARCH_IRQPRIO`, `tricore_irq_direct()` does not save `regs` in
`xcp.regs`, but `up_schedule_sigaction()` (tricore_schedulesigaction.c:88)
still uses `tcb->xcp.regs` for the running task. A signal sent from an
interrupt handler to the running task gets `saved_regs = NULL` and a signal
frame with SP 0 (`up_getusrsp(NULL)` returns 0 at irq.h:337), and
`tricore_irq_sched()` then overwrites `xcp.regs` with `regs`.
Fix: when the target is the running task and its regs are not saved, trigger
`TRICORE_SCHEDIRQ` and schedule the action there, as
arch/arm/src/armv7-m/arm_schedulesigaction.c does with PendSV.
##########
arch/tricore/src/common/tricore_irq.c:
##########
@@ -126,6 +142,112 @@ static void tricore_gpsrinitialize(void)
* Public Functions
****************************************************************************/
+/****************************************************************************
+ * Name: tricore_irq_to_srpn
+ *
+ * Description:
+ * Get the SRPN for an IRQ. If not yet assigned, auto-allocate the lowest
+ * available priority.
+ *
+ * Lookup searches the full range [MIN, MAX].
+ * Allocation range depends on CONFIG_ARCH_HIPRI_INTERRUPT:
+ * - Disabled: [MIN, MAX]
+ * - Enabled: [MIN, DISABLE_PRIORITY], SRPNs above DISABLE_PRIORITY
+ * are reserved for high-priority interrupts via up_prioritize_irq().
+ *
+ ****************************************************************************/
+
+int tricore_irq_to_srpn(int irq)
Review Comment:
`tricore_irq_to_srpn()` scans and writes `g_srpn_to_irq` with no lock;
`up_irq_to_ndx()`, which it replaces, took `g_irqlock`. Two `up_enable_irq()`
calls that overlap (SMP or a preempted task) can give the same SRPN to two IRQs.
Fix: keep `g_irqlock` around the scan and the write, and in
`up_prioritize_irq()`.
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