casaroli commented on code in PR #21355:
URL: https://github.com/apache/nuttx/pull/21355#discussion_r4470505156
##########
arch/tricore/include/irq.h:
##########
@@ -236,51 +233,74 @@ noinstrument_function static inline_function uintptr_t
up_getsp(void)
* Name: up_irq_save
*
* Description:
- * Disable interrupts and return the previous value of the mstatus register
+ * Disable interrupts and return the previous interrupt state.
+ *
+ * When CONFIG_ARCH_HIPRI_INTERRUPT is enabled, this raises ICR.CCPN
+ * to TRICORE_IRQ_DISABLE_PRIORITY so that high-priority interrupts
+ * (SRPN > TRICORE_IRQ_DISABLE_PRIORITY) remain unmasked. up_irq_save
+ * only raises CCPN, up_irq_restore only lowers it. This prevents the
+ * masking level from being accidentally lowered.
+ *
+ * Otherwise, uses the hardware disable instruction (ICR.IE = 0)
+ * for minimal overhead.
*
****************************************************************************/
noinstrument_function static inline_function irqstate_t up_irq_save(void)
{
+#ifdef CONFIG_ARCH_HIPRI_INTERRUPT
+ Ifx_CPU_ICR icr;
+ irqstate_t ccpn;
+
+ icr.U = tricore_mfcr(CPU_ICR);
+ ccpn = icr.B.CCPN;
+
+ if (TRICORE_IRQ_DISABLE_PRIORITY > ccpn)
Review Comment:
With `CONFIG_ARCH_HIPRI_INTERRUPT`, `up_irq_save()` raises CCPN to 250, but
`up_irq_enable()` (tricore_irq.c:154) still sets only ICR.IE and leaves CCPN at
250. `tricore_sigdeliver()` runs `up_irq_save()` and then `goto retry` to
`up_irq_enable()`, so the next signal handler runs with all normal interrupts
masked.
Fix: in `up_irq_enable()`, under `CONFIG_ARCH_HIPRI_INTERRUPT`, also set
ICR.CCPN to 0.
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