casaroli opened a new pull request, #21459: URL: https://github.com/apache/nuttx/pull/21459
## Summary The i.MX6 never calls up_perf_init(), so the PMU cycle counter does not run and its rate stays ULONG_MAX. With ARCH_PERF_EVENTS (the default with SCHED_CRITMONITOR) all perf times are 0, and ostest perf_gettime_test fails. This PR calls up_perf_init() at the end of arm_boot() and arm_perf_secondary_init() in arm_cpu_boot(), as the qemu, goldfish and rtl8730e chips do. The rate is the CPU clock. NuttX keeps the clock from U-Boot, which board.h and imx_clockconfig.c give as 792 MHz, so board.h gets BOARD_CPU_FREQUENCY with this value. up_perf_init(0) is not correct here: it reads CNTFRQ, and the Cortex-A9 has no generic timer. ## Impact i.MX6 with ARCH_PERF_EVENTS only. An i.MX6 board outside the tree must define BOARD_CPU_FREQUENCY when it enables ARCH_PERF_EVENTS. The rate does not follow a CPU clock change: NuttX does not change the clock on this chip. No API change, no documentation change. ## Testing QEMU sabrelite (`-M sabrelite`, the machine of sabre-6quad:citest), TCG, SCHED_CRITMONITOR and ARCH_PERF_EVENTS: | Test | master | this PR | |---|---|---| | sabre-6quad:nsh ostest | status 256 (perf_gettime_test: time not monotonically increasing) | status 0 | | sabre-6quad:smp ostest, 4 CPUs | status 256 (same) | status 0 | | sabre-6quad:smp, CPU time of a busy loop of 500 ms, CPU 0 to 3 | 0, 0, 0, 0 ms | 756, 747, 762, 759 ms | | sabre-6quad:nsh, CPU time of a busy loop of 200 ms | 0 ms | 312 ms | The counter now runs on all CPUs. QEMU cannot confirm the rate. Its PMU counts at 1 GHz, not 792 MHz (factor 1.26), and its GPT is slow compared to the 66 MHz that imx_timerisr.c expects: NSH `sleep 10` takes 12.35 s of host time, against 10.00 s on qemu-armv7a:nsh (factor 1.235). Together this gives 1.56, the 312 ms above. Real hardware was not available. Builds with -Werror: all sabre-6quad configurations (citest, coredump, elf, knsh, knsh_smp, libcxx, netknsh, netknsh_smp, netnsh, netnsh_ar8031, netnsh_smp, netnsh_wb, nsh, posix_spawn, smp). With ARCH_PERF_EVENTS too: nsh, smp, knsh, knsh_smp, netnsh_smp. CMake: coredump, nsh, smp (the configurations of arm-imx.dat). The runs and builds are on 39a1f27900c. After the rebase on 3d57048f1e1, the sabre-6quad:smp run gives the same result: 787, 779, 776, 776 ms, ostest status 0. The branch is now rebased on f19dbe6f6d3 (no change in the touched files). -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
