casaroli commented on code in PR #21406:
URL: https://github.com/apache/nuttx/pull/21406#discussion_r4470511378
##########
boards/arm/stm32n6/stm32n6570-dk/Kconfig:
##########
@@ -5,4 +5,12 @@
if ARCH_BOARD_STM32N6570_DK
+config STM32N6570_DK_CLOCK_HSI
Review Comment:
This option runs the CPU at 200 MHz but `CONFIG_BOARD_LOOPSPERMSEC` stays at
84000, the value this PR sets for 800 MHz (it was 21000 at 200 MHz), so delay
loops run about 4 times too long.
Fix: say in the help text to set `CONFIG_BOARD_LOOPSPERMSEC=21000` with this
option.
##########
Documentation/platforms/arm/stm32n6/index.rst:
##########
@@ -26,14 +26,16 @@ The following list indicates peripherals supported in NuttX:
Peripheral Support Notes
========== ======= ===============================================
GPIO Yes
-PWR Yes Partial.
-RCC Yes PLL1 clock tree.
+EXTI Yes GPIO interrupts through the common driver.
+DMA Yes GPDMA1 and HPDMA1 through the common GPDMA driver.
Review Comment:
The common GPDMA driver never sets the channel security attributes: it does
not write SECCFGR or PRIVCFGR, or set SSEC or DSEC itself. ST's N6 FSBL
examples (for example UART_TwoBoards_ComDMA) set
`DMA_CHANNEL_SEC|DMA_CHANNEL_PRIV|DMA_CHANNEL_SRC_SEC|DMA_CHANNEL_DEST_SEC` on
the channels, and this port also uses the secure aliases. No N6 driver uses DMA
yet and the PR text shows no transfer test, so "Yes" here is untested.
Fix: set these attributes for N6 in `stm32_dma_gpdma.c` and test a transfer,
or mark DMA as untested in this table.
##########
arch/arm/src/stm32n6/hardware/stm32n6xxx_rcc.h:
##########
@@ -361,26 +2056,81 @@
RCC_APB1LLPENR_TIM12LPEN |
RCC_APB1LLPENR_TIM13LPEN | \
RCC_APB1LLPENR_TIM14LPEN)
+/* APB1 sleep enable register 2 (APB1HLPENR) */
+
+#define RCC_APB1HLPENR_MDIOSLPEN (1 << 5) /* Bit 5: MDIOS enable in
+ * Sleep mode */
+#define RCC_APB1HLPENR_FDCANLPEN (1 << 8) /* Bit 8: FDCAN enablein
+ * Sleep mode */
+#define RCC_APB1HLPENR_UCPD1LPEN (1 << 18) /* Bit 18: UCPD1 enable in
+ * Sleep mode */
+
/* APB2 peripheral clock enable in Sleep mode */
-#define RCC_APB2LPENR_TIM9LPEN (1 << 19) /* Bit 19: TIM9 enable in
CSLEEP */
-#define RCC_APB2LPENR_TIM17LPEN (1 << 18) /* Bit 18: TIM17 enable in
CSLEEP */
-#define RCC_APB2LPENR_TIM16LPEN (1 << 17) /* Bit 17: TIM16 enable in
CSLEEP */
-#define RCC_APB2LPENR_TIM15LPEN (1 << 16) /* Bit 16: TIM15 enable in
CSLEEP */
-#define RCC_APB2LPENR_TIM18LPEN (1 << 15) /* Bit 15: TIM18 enable in
CSLEEP */
-#define RCC_APB2LPENR_USART1LPEN (1 << 4) /* Bit 4: USART1 enable in
CSLEEP */
-#define RCC_APB2LPENR_TIM8LPEN (1 << 1) /* Bit 1: TIM8 enable in
CSLEEP */
-#define RCC_APB2LPENR_TIM1LPEN (1 << 0) /* Bit 0: TIM1 enable in
CSLEEP */
+#define RCC_APB2LPENR_TIM1LPEN (1 << 0) /* Bit 0: TIM1 enable in
+ * CSLEEP */
+#define RCC_APB2LPENR_TIM8LPEN (1 << 1) /* Bit 1: TIM8 enable in
+ * CSLEEP */
+#define RCC_APB2LPENR_USART1LPEN (1 << 4) /* Bit 4: USART1 enable in
+ * CSLEEP */
+#define RCC_APB2LPENR_USART6LPEN (1 << 5) /* Bit 5: USART6 enable */
+#define RCC_APB2LPENR_UART9LPEN (1 << 6) /* Bit 6: UART9 enable */
+#define RCC_APB2LPENR_USART10LPEN (1 << 7) /* Bit 7: USART10 enable */
+#define RCC_APB2LPENR_SPI1LPEN (1 << 12) /* Bit 12: SPI1 enable */
+#define RCC_APB2LPENR_SPI4LPEN (1 << 13) /* Bit 13: SPI4 enable */
+#define RCC_APB2LPENR_TIM18LPEN (1 << 15) /* Bit 15: TIM18 enable in
+ * CSLEEP */
+#define RCC_APB2LPENR_TIM15LPEN (1 << 16) /* Bit 16: TIM15 enable in
+ * CSLEEP */
+#define RCC_APB2LPENR_TIM16LPEN (1 << 17) /* Bit 17: TIM16 enable in
+ * CSLEEP */
+#define RCC_APB2LPENR_TIM17LPEN (1 << 18) /* Bit 18: TIM17 enable in
+ * CSLEEP */
+#define RCC_APB2LPENR_TIM9LPEN (1 << 19) /* Bit 19: TIM9 enable in
+ * CSLEEP */
+#define RCC_APB2LPENR_SPI5LPEN (1 << 20) /* Bit 20: SPI5 enable */
+#define RCC_APB2LPENR_SAI1LPEN (1 << 21) /* Bit 21: SAI1 enable */
+#define RCC_APB2LPENR_SAI2LPEN (1 << 22) /* Bit 22: SAI2 enable */
#define RCC_APB2LPENR_ALLTIM (RCC_APB2LPENR_TIM1LPEN |
RCC_APB2LPENR_TIM8LPEN | \
RCC_APB2LPENR_TIM9LPEN |
RCC_APB2LPENR_TIM15LPEN | \
RCC_APB2LPENR_TIM16LPEN |
RCC_APB2LPENR_TIM17LPEN | \
RCC_APB2LPENR_TIM18LPEN)
-/* Peripheral kernel clock select register 13 */
+/* APB3 sleep enable register (APB3LPENR) */
-#define RCC_CCIPR13_USART1SEL_SHIFT (0)
-#define RCC_CCIPR13_USART1SEL_MASK (0x7 << RCC_CCIPR13_USART1SEL_SHIFT)
-#define RCC_CCIPR13_USART1SEL_HSI (6 << RCC_CCIPR13_USART1SEL_SHIFT)
+#define RCC_APB3LPENR_DFTLPEN (1 << 2) /* Bit 2: DFT enable */
+
+/* APB4 sleep enable register 1 (APB4LLPENR) */
+
+#define RCC_APB4LLPENR_HDPLPEN (1 << 2) /* Bit 2: HDP enable */
+#define RCC_APB4LLPENR_LPUART1LPEN (1 << 3) /* Bit 3: LPUART1 enable */
+#define RCC_APB4LLPENR_SPI6LPEN (1 << 5) /* Bit 5: SPI6 enable */
+#define RCC_APB4LLPENR_I2C4LPEN (1 << 7) /* Bit 7: I2C4 enable */
+#define RCC_APB4LLPENR_LPTIM2LPEN (1 << 9) /* Bit 9: LPTIM2 enable */
+#define RCC_APB4LLPENR_LPTIM3LPEN (1 << 10) /* Bit 10: LPTIM3 enable */
+#define RCC_APB4LLPENR_LPTIM4LPEN (1 << 11) /* Bit 11: LPTIM4 enable */
+#define RCC_APB4LLPENR_LPTIM5LPEN (1 << 12) /* Bit 12: LPTIM5 enable */
Review Comment:
Master now uses `RCC_APB4LLPENR_ALLLPTIM` in `stm32_start.c` under
`CONFIG_STM32_LPTIM`, and this rewrite of the header drops it, so the rebase
can auto-merge `stm32_start.c` and still fail to compile. No N6 defconfig
enables LPTIM, so CI will not show it.
Fix: keep the `RCC_APB4LLPENR_ALLLPTIM` define after the
`RCC_APB4LLPENR_LPTIM5LPEN` line when you resolve the conflict.
##########
boards/arm/stm32n6/stm32n6570-dk/configs/nsh/defconfig:
##########
@@ -32,6 +37,9 @@ CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_WAITPID=y
CONFIG_STM32N6_DEBUG=y
+CONFIG_STM32_DMA1=y
CONFIG_STM32_USART1=y
CONFIG_SYSTEM_NSH=y
CONFIG_USART1_SERIAL_CONSOLE=y
+CONFIG_USERLED=y
Review Comment:
`/dev/userleds` is never registered in this config. `CONFIG_ARCH_LEDS` stays
at its default `y`, so `stm32_bringup.c:77` skips `userled_lower_initialize()`
and `Make.defs` builds `stm32_autoleds.c`; the linked image has no
`board_userled` or `userled_lower_initialize`, but the board's `index.rst:114`
says the LEDs are available there.
Fix: add `# CONFIG_ARCH_LEDS is not set` to this defconfig.
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