zkkkk12 opened a new pull request, #21484:
URL: https://github.com/apache/nuttx/pull/21484
## Summary
This series adds a PHY abstraction layer (PHYLIB) to NuttX's netdev
lower-half framework, plus two Realtek PHY drivers built on it.
Motivation: Ethernet MAC drivers currently each re-implement their own PHY
handling (link detection, autoneg, register polling). This duplicates code
and makes it hard to reuse a PHY across different MACs. PHYLIB provides a
shared PHY device model and state machine so MAC drivers only wire up the
MDIO bus and let the framework manage the PHY.
The series is split into 5 self-contained commits (each builds on its own):
1. **net/mdio: extend MDIO bus with Clause 45 access and reset level
control**
- Adds `mdio_c45_read()/mdio_c45_write()` for Clause 45 MMD register
access, using native C45 ops when available and falling back to
indirect access over C22 registers 13/14.
- Changes the reset op to level control (assert/deassert by value) with
idempotency tracked in `reset_state`.
2. **net/phy: add PHY abstraction layer (PHYLIB) framework**
- PHY device lifecycle (create/free/scan), connect/disconnect, and a
poll/interrupt-driven state machine.
- Generic C22/C45 PHY drivers as fallbacks, register access helpers, and
upper-half `ethtool`/ioctl integration via `phy_ioctl()`.
- New Kconfig: `CONFIG_NET_PHYLIB` (default n) with poll interval and
max driver/device limits.
3. **net/phy: add Realtek RTL8221B PHY driver** — 2.5Gbps multi-gig PHY,
including firmware ramcode tables and paged register handling.
4. **net/phy: 100BASE-T1 modes and paged register access** — adds
100/1000BASE-T1 link-mode bits, paged register helpers
(`phy_read_paged`/`phy_write_paged`/`phy_modify_paged`) with bus locking,
and lockless MDIO primitives.
5. **net/phy: add RTL9000B 100BASE-T1 PHY driver** — automotive single-pair
Ethernet PHY, with DSP/config verification tables.
### Advantages
As a generic PHY framework (an independent subsystem rather than a
lightweight PHY hook embedded in a single MAC driver), PHYLIB provides:
| Dimension | PHYLIB capability |
|-----------|-------------------|
| Positioning | Independent subsystem (`CONFIG_NET_PHYLIB`), not tied to any
specific MAC driver |
| PHY driver callbacks | 8 callbacks: `config_init` / `config_aneg` /
`read_status` / `config_power` / `config_intr` / `handle_interrupt` /
`read_page` / `write_page` |
| Negotiation / speed resolution | Done in the PHY driver's `read_status`,
MAC-independent |
| Cross-MAC reuse | Write a PHY driver once; any MAC on an MDIO bus can
reuse it without re-implementing negotiation |
| Link state machine | 7 states: `DOWN / READY / UP / RUNNING / NOLINK /
HALTED / ERROR` |
| Lifecycle | Full `connect` / `disconnect` / `start` / `stop` |
| Interrupt modes | Three modes: `PHY_POLL` / `PHY_MAC_INTERRUPT` (MAC owns
the line) / real PHY IRQ (framework attaches its own ISR), with automatic
fallback to polling if IRQ attach fails |
| Link-loss detection latency | Immediate in interrupt mode; bounded by
`CONFIG_NET_PHYLIB_POLL_INTERVAL` (default 1000 ms) in polling mode |
| Paged register access | `phy_read_paged` / `phy_write_paged` /
`phy_modify_paged` hold `mdio_lock` across the whole "select page -> access ->
restore page" sequence, atomic against MII ioctl, with restore failures
propagated |
| PHY identification | Automatic `phy_id & phy_id_mask` matching with
generic C22/C45 fallback; no board-level hardcoded IDs |
| C45 / MMD | Full `phy_read_mmd` etc., native C45 preferred with indirect
access over C22 regs 13/14 as fallback |
| Multi-gig PHYs | Supports 2.5G/5G/10G-class PHYs (RTL8221B 2.5G included) |
| ethtool integration | `ETHTOOL_GLINKSETTINGS` / `SLINKSETTINGS` /
`NWAY_RST` / `GLINK` |
| MII ioctl | Unified `phy_ioctl` in the framework; MACs need not each
implement it |
| PHY reset line | `mdio_ops.reset` callback + idempotent `phy_reset` (level
control, assert/deassert) |
| RGMII delay | Expressed via `phydev->interface` (`RGMII_ID` / `TXID` /
`RXID` etc.) rather than hardcoded per driver |
| Power management | `config_power` (PHY PDOWN bit) |
| Concurrency / SMP | Per-device lock, explicitly handling the
ioctl-vs-state-machine AB-BA deadlock and slot-reuse race |
| Vendor driver examples | RTL8221B (firmware patch / SerDes / C45) and
RTL9000B (100BASE-T1) |
### Limitations
| Dimension | Notes |
|-----------|-------|
| Code size per PHY | Larger than an embedded lightweight hook (~130 lines,
zero deps); requires understanding the subsystem |
| Learning curve | Requires understanding the `phy_driver_s` callback model
and MDIO lower-half integration |
| ethtool coverage | Only the commands needed by current drivers; still a
subset of the full ethtool command set |
| Single-word link-mode mask | Each link-mode mask currently uses one 32-bit
word, limiting the number of representable modes |
| Existing drivers not migrated | In-tree MAC drivers have not yet been
migrated to PHYLIB |
| Static capacity limits | PHY driver/device counts bounded by
`CONFIG_NET_PHYLIB_MAX_DRIVERS` / `MAX_PHYS` (default 8 each) |
| Vendor driver count | Only RTL8221B / RTL9000B so far |
## Impact
- **Users**: No impact by default. All new code is gated behind
`CONFIG_NET_PHYLIB=n` and the per-driver `CONFIG_NET_PHY_REALTEK_*`
options,
all defaulting to `n`. Existing MAC drivers are unaffected.
- **Build**: New sources under `drivers/net/phy/` only compile when
`CONFIG_NET_PHYLIB=y`. Both Make and CMake build systems updated.
- **API**: Adds a new public header section in `include/nuttx/net/phy.h` and
`include/nuttx/net/realtek_phy.h`. Extends `struct netdev_lowerhalf_s` and
`struct ethtool_ops_s`. The MDIO `reset` op signature changed (now takes a
level value) — affects any in-tree MDIO lower-half (updated here).
- **Hardware**: Enables RTL8221B (2.5G) and RTL9000B (100BASE-T1) PHYs.
- **Security / Compatibility**: No security impact. Backward compatible when
the feature is disabled.
## Testing
Verified on hardware that the PHYLIB state machine correctly tracks the
physical link. With the Ethernet cable unplugged the interface stays in the
`UP` (administratively up, no carrier) state; once the cable is plugged in,
the RTL8221B PHY reports link up and the interface transitions to `RUNNING`
(carrier present). TX counters advance after the link comes up.
**Host machine:** Ubuntu 22.04 x86_64
**Target board:** Infineon AURIX TC4 platform
**PHY:** Realtek RTL8221B (`CONFIG_NET_PHY_REALTEK_RTL8221B=y`,
`CONFIG_NET_PHYLIB=y`)
**How tested:** Ran `ifconfig` with the cable unplugged and then plugged in,
and observed the interface state change from `UP` to `RUNNING`, confirming
the PHYLIB link-state machine detects carrier via the RTL8221B driver.
**Logs** (`ifconfig`, cable unplugged → plugged, state `UP` → `RUNNING`):
eth0.45 Link encap:Ethernet HWaddr 02:04:00:00:04:11 at **UP** mtu 1500
inet addr:[172.16.45.139](http://172.16.45.139/)
DRaddr:[0.0.0.0](http://0.0.0.0/) Mask:[255.255.255.0](http://255.255.255.0/)
RX: Received Fragment Errors Bytes
00000000 00000000 00000000 0
IPv4 ARP Dropped
00000000 00000000 00000000
TX: Queued Sent Errors Timeouts Bytes
00000002 00000050 00000000 00000000 5c
Total Errors: 00000000
IPv4 TCP UDP ICMP
Received 0000 0000 0000 0000
Dropped 0000 0000 0000 0000
IPv4 VHL: 0000 Frg: 0000
Checksum 0000 0000 0000 0000
TCP ACK: 0000 SYN: 0000
RST: 0000 0000
HDR: 0000
Type 0000 ---- ---- 0000
Sent 0034 0000 0032 0000
Rexmit ---- 0000 ---- ----
eth0.45 Link encap:Ethernet HWaddr 02:04:00:00:04:11 at **RUNNING** mtu 1500
inet addr:[172.16.45.139](http://172.16.45.139/)
DRaddr:[0.0.0.0](http://0.0.0.0/) Mask:[255.255.255.0](http://255.255.255.0/)
RX: Received Fragment Errors Bytes
00000000 00000000 00000000 0
IPv4 ARP Dropped
00000000 00000000 00000000
TX: Queued Sent Errors Timeouts Bytes
00000002 00000080 00000000 00000000 5c
Total Errors: 00000000
IPv4 TCP UDP ICMP
Received 0000 0000 0000 0000
Dropped 0000 0000 0000 0000
IPv4 VHL: 0000 Frg: 0000
Checksum 0000 0000 0000 0000
TCP ACK: 0000 SYN: 0000
RST: 0000 0000
HDR: 0000
Type 0000 ---- ---- 0000
Sent 003f 0000 003d 0000
Rexmit ---- 0000 ---- ----
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