raiden00pl commented on code in PR #21400: URL: https://github.com/apache/nuttx/pull/21400#discussion_r4465061825
########## boards/arm/stm32h7/nucleo-h7s3l8/include/board.h: ########## @@ -57,72 +65,109 @@ #define STM32_LSI_FREQUENCY 32000ul #define STM32_LSE_FREQUENCY 32768ul -/* Main PLL configuration - * - * The HSI and HSE configurations both produce a 600 MHz PLL1 VCO and use - * PLL1P as the system clock: +/* PLL clocking is derived from pll_ck in put source divided by + * PLL DIVM divisor then multiplied by DIVM divisor: * - * HSI: PLL1_VCO = (64 MHz / 32) * 300 = 600 MHz - * HSE: PLL1_VCO = (24 MHz / 2) * 50 = 600 MHz - * - * PLL1P = 600 MHz - * PLL1Q = 300 MHz - * PLL1R = 300 MHz + * VCOx = (pll_ck / DIVNx) * DIVMx */ -#ifdef CONFIG_NUCLEO_H7S3L8_USE_HSE +/* Define pll_ck clock source and frequency */ + +#ifdef CONFIG_STM32H7S8_DK_USE_HSE Review Comment: why are you using DK definitions in nucleo board ??? -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
