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commit bf565734230b41043acc7035f9cb8190cd11bcd1 Author: iamadahn <[email protected]> AuthorDate: Fri Nov 6 15:19:49 2026 +0300 board/arm/stm32g0/weact-stm32g0b1: Add DroneCAN configuration. Add a DroneCAN example configuration using FDCAN1 in Classic CAN mode at 1 Mbit/s on PD0/PD1 with node ID 42. Assisted-by: Codex:GPT-6-Astra Signed-off-by: iamadahn <[email protected]> --- .../arm/stm32g0/boards/weact-stm32g0b1/index.rst | 4 ++ .../weact-stm32g0b1/configs/dronecan/defconfig | 60 ++++++++++++++++++++++ boards/arm/stm32g0/weact-stm32g0b1/include/board.h | 10 ++++ 3 files changed, 74 insertions(+) diff --git a/Documentation/platforms/arm/stm32g0/boards/weact-stm32g0b1/index.rst b/Documentation/platforms/arm/stm32g0/boards/weact-stm32g0b1/index.rst index 6311e8d0a00..a384f965306 100644 --- a/Documentation/platforms/arm/stm32g0/boards/weact-stm32g0b1/index.rst +++ b/Documentation/platforms/arm/stm32g0/boards/weact-stm32g0b1/index.rst @@ -67,3 +67,7 @@ buttons This is a config example to test onboard user button with input driver and buttons example in signal mode. +dronecan +-------- + +This configuration enables the DroneCAN example on FDCAN1 at 1 Mbit/s. diff --git a/boards/arm/stm32g0/weact-stm32g0b1/configs/dronecan/defconfig b/boards/arm/stm32g0/weact-stm32g0b1/configs/dronecan/defconfig new file mode 100644 index 00000000000..e98b7f0eff9 --- /dev/null +++ b/boards/arm/stm32g0/weact-stm32g0b1/configs/dronecan/defconfig @@ -0,0 +1,60 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="weact-stm32g0b1" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_WEACT_STM32G0B1=y +CONFIG_ARCH_CHIP="stm32g0" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G0=y +CONFIG_ARCH_CHIP_STM32G0B1CB=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=4164 +CONFIG_BUILTIN=y +CONFIG_CANUTILS_LIBDRONECAN=y +CONFIG_CAN_ERRORS=y +CONFIG_CAN_EXTID=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y +CONFIG_EXAMPLES_DRONECAN=y +CONFIG_EXAMPLES_DRONECAN_NODE_ID=42 +CONFIG_EXAMPLES_HELLO=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1536 +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=64 +CONFIG_NSH_READLINE=y +CONFIG_NUNGET_CHARS=0 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 +CONFIG_PTHREAD_MUTEX_UNSAFE=y +CONFIG_PTHREAD_STACK_DEFAULT=1536 +CONFIG_RAM_SIZE=147456 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=19 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2013 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_STM32_FDCAN1=y +CONFIG_STM32_FDCAN1_BITRATE=1000000 +CONFIG_STM32_FDCAN1_NTSEG1=13 +CONFIG_STM32_FDCAN1_NTSEG2=2 +CONFIG_STM32_PWR=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32g0/weact-stm32g0b1/include/board.h b/boards/arm/stm32g0/weact-stm32g0b1/include/board.h index 033ea7ffbde..712b53d58d1 100644 --- a/boards/arm/stm32g0/weact-stm32g0b1/include/board.h +++ b/boards/arm/stm32g0/weact-stm32g0b1/include/board.h @@ -118,6 +118,11 @@ #define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) +/* FDCAN uses PCLK1 (32 MHz), with CKDIV set to divide by one. */ + +#define STM32_FDCAN_SEL RCC_CCIPR2_FDCANSEL_PCLK +#define STM32_FDCAN_FREQUENCY STM32_PCLK1_FREQUENCY + /* Timers will receive PCLK1 * 2 */ #define STM32_TIM1_CLKIN (2 * STM32_PCLK1_FREQUENCY) @@ -192,4 +197,9 @@ #define GPIO_USART3_RX (GPIO_USART3_RX_3|GPIO_SPEED_HIGH) /* PB9 */ #define GPIO_USART3_TX (GPIO_USART3_TX_3|GPIO_SPEED_HIGH) /* PB8 */ +/* FDCAN1 */ + +#define GPIO_FDCAN1_RX (GPIO_FDCAN1_RX_3|GPIO_SPEED_HIGH) /* PD0 */ +#define GPIO_FDCAN1_TX (GPIO_FDCAN1_TX_3|GPIO_SPEED_HIGH) /* PD1 */ + #endif /* __BOARDS_ARM_STM32F0L0G0_WEACT_STM32G0B1_INCLUDE_BOARD_H */
