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commit f3ec9a15b5b07c5f5f8c1020bfb3b976305e5b5f Author: Parthiban Nallathambi <[email protected]> AuthorDate: Thu Nov 5 15:53:48 2026 +0530 arch/tricore: Replace the iLLD trap vector table. The trap vectors came from the iLLD IfxCpu_Trap.c, which reached tricore_trapcall and tricore_svcall through the hook macros in Ifx_Cfg_Trap.h and passed them the iLLD IfxCpu_Trap record. Add NuttX's own per-core tables in gnu/tricore_vectors.S and its TASKING twin. They enter the handlers in the same state, so the handlers still see PCXI at the lower context of the trapped code, and pass a struct tricore_trap_s. Drop IfxCpu_Trap.c, Ifx_Cfg_Trap.h and IFX_CFG_EXTEND_TRAP_HOOKS. Co-authored-by: Saravanan Sekar <[email protected]> Signed-off-by: Parthiban Nallathambi <[email protected]> --- arch/tricore/include/csfr.h | 1 + arch/tricore/src/common/CMakeLists.txt | 11 ++- arch/tricore/src/common/Ifx_Cfg_Trap.h | 94 ---------------------- arch/tricore/src/common/Make.defs | 10 ++- arch/tricore/src/common/gnu/tricore_vectors.S | 94 ++++++++++++++++++++++ .../tricore/src/common/tasking/tricore_vectors.asm | 89 ++++++++++++++++++++ arch/tricore/src/common/tricore_internal.h | 13 +++ arch/tricore/src/common/tricore_trapcall.c | 15 ++-- arch/tricore/src/tc3xx/CMakeLists.txt | 1 - arch/tricore/src/tc3xx/Make.defs | 1 - arch/tricore/src/tc4xx/CMakeLists.txt | 1 - arch/tricore/src/tc4xx/Make.defs | 1 - 12 files changed, 221 insertions(+), 110 deletions(-) diff --git a/arch/tricore/include/csfr.h b/arch/tricore/include/csfr.h index 23ecff36aa0..84d3b6c5eca 100644 --- a/arch/tricore/include/csfr.h +++ b/arch/tricore/include/csfr.h @@ -35,6 +35,7 @@ #define TRICORE_CPU_PCXI 0xfe00 /* Previous Context Information */ #define TRICORE_CPU_PSW 0xfe04 /* Program Status Word */ +#define TRICORE_CPU_CORE_ID 0xfe1c /* Core Identification */ #define TRICORE_CPU_ICR 0xfe2c /* Interrupt Control Register */ #define TRICORE_CPU_FCX 0xfe38 /* Free CSA List Head Pointer */ diff --git a/arch/tricore/src/common/CMakeLists.txt b/arch/tricore/src/common/CMakeLists.txt index 57e54c8af1f..6b1bb034d83 100644 --- a/arch/tricore/src/common/CMakeLists.txt +++ b/arch/tricore/src/common/CMakeLists.txt @@ -65,10 +65,19 @@ if(CONFIG_ARCH_HAVE_DEBUG) list(APPEND SRCS tricore_hwdebug.c) endif() -set(IFXFLAGS -DIFX_CFG_EXTEND_TRAP_HOOKS -DIFX_USE_SW_MANAGED_INT) +set(IFXFLAGS -DIFX_USE_SW_MANAGED_INT) target_sources(arch PRIVATE ${SRCS}) target_sources(nuttx PRIVATE tricore_doirq.c) + +# The trap vectors are placed by the linker script and not referenced by symbol, +# link them directly instead of from the archive. + +if(CONFIG_TRICORE_TOOLCHAIN_TASKING) + target_sources(nuttx PRIVATE tasking/tricore_vectors.${ASMEXT}) +else() + target_sources(nuttx PRIVATE gnu/tricore_vectors.${ASMEXT}) +endif() target_compile_options(arch PRIVATE ${IFXFLAGS}) target_compile_options(nuttx PRIVATE ${IFXFLAGS}) target_include_directories( diff --git a/arch/tricore/src/common/Ifx_Cfg_Trap.h b/arch/tricore/src/common/Ifx_Cfg_Trap.h deleted file mode 100644 index b014457689d..00000000000 --- a/arch/tricore/src/common/Ifx_Cfg_Trap.h +++ /dev/null @@ -1,94 +0,0 @@ -/**************************************************************************** - * arch/tricore/src/common/Ifx_Cfg_Trap.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_TRICORE_SRC_COMMON_IFX_CFG_TRAP_H -#define __ARCH_TRICORE_SRC_COMMON_IFX_CFG_TRAP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include <nuttx/config.h> - -#include "tricore_internal.h" - -#if (IFX_CFG_EXTEND_TRAP_HOOKS == 1) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Trap Hook definition */ - -/* Trap Call */ - -#define IFX_CFG_CPU_TRAP_COMMON_HOOK(trapWatch) \ - do \ - { \ - Ifx__moveToAddrParam0((void *)&trapWatch); \ - Ifx__jumpToFunctionWithLink(tricore_trapcall); \ - } \ - while (0) - -#define IFX_CFG_CPU_TRAP_SYSCALL_HOOK(trapWatch) \ - do \ - { \ - Ifx__moveToAddrParam0((void *)&trapWatch); \ - Ifx__jumpToFunctionWithLink(tricore_svcall); \ - } \ - while (0) - -#define IFX_CFG_CPU_TRAP_TSR_HOOK(trapWatch) \ - IFX_CFG_CPU_TRAP_COMMON_HOOK(trapWatch) -#define IFX_CFG_CPU_TRAP_NMI_HOOK(trapWatch) \ - IFX_CFG_CPU_TRAP_COMMON_HOOK(trapWatch) -#define IFX_CFG_CPU_TRAP_MME_HOOK(trapWatch) \ - IFX_CFG_CPU_TRAP_COMMON_HOOK(trapWatch) -#define IFX_CFG_CPU_TRAP_IPE_HOOK(trapWatch) \ - IFX_CFG_CPU_TRAP_COMMON_HOOK(trapWatch) -#define IFX_CFG_CPU_TRAP_IE_HOOK(trapWatch) \ - IFX_CFG_CPU_TRAP_COMMON_HOOK(trapWatch) -#define IFX_CFG_CPU_TRAP_CME_HOOK(trapWatch) \ - IFX_CFG_CPU_TRAP_COMMON_HOOK(trapWatch) -#define IFX_CFG_CPU_TRAP_BE_HOOK(trapWatch) \ - IFX_CFG_CPU_TRAP_COMMON_HOOK(trapWatch) -#define IFX_CFG_CPU_TRAP_ASSERT_HOOK(trapWatch) \ - IFX_CFG_CPU_TRAP_COMMON_HOOK(trapWatch) - -#define IFX_CFG_CPU_TRAP_SYSCALL_CPU0_HOOK(trapWatch) \ - IFX_CFG_CPU_TRAP_SYSCALL_HOOK(trapWatch) -#define IFX_CFG_CPU_TRAP_SYSCALL_CPU1_HOOK(trapWatch) \ - IFX_CFG_CPU_TRAP_SYSCALL_HOOK(trapWatch) -#define IFX_CFG_CPU_TRAP_SYSCALL_CPU2_HOOK(trapWatch) \ - IFX_CFG_CPU_TRAP_SYSCALL_HOOK(trapWatch) -#define IFX_CFG_CPU_TRAP_SYSCALL_CPU3_HOOK(trapWatch) \ - IFX_CFG_CPU_TRAP_SYSCALL_HOOK(trapWatch) -#define IFX_CFG_CPU_TRAP_SYSCALL_CPU4_HOOK(trapWatch) \ - IFX_CFG_CPU_TRAP_SYSCALL_HOOK(trapWatch) -#define IFX_CFG_CPU_TRAP_SYSCALL_CPU5_HOOK(trapWatch) \ - IFX_CFG_CPU_TRAP_SYSCALL_HOOK(trapWatch) -#define IFX_CFG_CPU_TRAP_SYSCALL_CPU6_HOOK(trapWatch) \ - IFX_CFG_CPU_TRAP_SYSCALL_HOOK(trapWatch) - -#endif /* IFX_CFG_EXTEND_TRAP_HOOKS */ - -#endif /* __ARCH_TRICORE_SRC_COMMON_IFX_CFG_TRAP_H */ diff --git a/arch/tricore/src/common/Make.defs b/arch/tricore/src/common/Make.defs index 716031ca1d4..3e6ba29da03 100644 --- a/arch/tricore/src/common/Make.defs +++ b/arch/tricore/src/common/Make.defs @@ -46,6 +46,15 @@ CMN_CSRCS += tricore_trapcall.c CMN_CSRCS += tricore_systimer.c CMN_CSRCS += tricore_usestack.c +ifeq ($(CONFIG_TRICORE_TOOLCHAIN_TASKING),y) + TRICORE_SUBDIR = tasking +else + TRICORE_SUBDIR = gnu +endif + +HEAD_ASRC += tricore_vectors$(ASMEXT) +VPATH += common$(DELIM)$(TRICORE_SUBDIR) + ifeq ($(CONFIG_SCHED_BACKTRACE),y) CMN_CSRCS += tricore_backtrace.c endif @@ -66,7 +75,6 @@ ifeq ($(CONFIG_ARCH_HAVE_DEBUG),y) CMN_CSRCS += tricore_hwdebug.c endif -CFLAGS += -DIFX_CFG_EXTEND_TRAP_HOOKS CFLAGS += -DIFX_USE_SW_MANAGED_INT # TASKING toolchain: build a fake libc_fpu.a to override the toolchain's diff --git a/arch/tricore/src/common/gnu/tricore_vectors.S b/arch/tricore/src/common/gnu/tricore_vectors.S new file mode 100644 index 00000000000..6d31a6e1b8a --- /dev/null +++ b/arch/tricore/src/common/gnu/tricore_vectors.S @@ -0,0 +1,94 @@ +/**************************************************************************** + * arch/tricore/src/common/gnu/tricore_vectors.S + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Trap vector table, one per core. BTV points at the table of the core in + * use; the linker script keeps the .traptab_cpuN section of that core. + * + * Each 32-byte slot saves the lower context and enters the common trap + * entry with the trap class in %d5; the hardware has put the TIN in %d15 + * and the trap return address in %a11. The entry builds a struct + * tricore_trap_s on the stack and enters the handler with jli, so the + * handler sees PCXI pointing at the lower context of the trapped code. + * The handler returns with ji %a11, then the entry restores the lower + * context and returns from the trap. + * + * tasking/tricore_vectors.asm is the same code in the TASKING syntax. + ****************************************************************************/ + +#include <arch/csfr.h> + + .macro TRAPSLOT cls, entry + svlcx + mov %d5, \cls + j \entry + .p2align 5 + .endm + + .macro TRAPTAB cpu + .section .traptab_cpu\cpu, "ax", %progbits + .p2align 8 + .global tricore_trap_vectors_cpu\cpu +tricore_trap_vectors_cpu\cpu: + TRAPSLOT 0, tricore_trap_entry + TRAPSLOT 1, tricore_trap_entry + TRAPSLOT 2, tricore_trap_entry + TRAPSLOT 3, tricore_trap_entry + TRAPSLOT 4, tricore_trap_entry + TRAPSLOT 5, tricore_trap_entry + TRAPSLOT 6, tricore_syscall_entry + TRAPSLOT 7, tricore_trap_entry + .endm + + TRAPTAB 0 + TRAPTAB 1 + TRAPTAB 2 + TRAPTAB 3 + TRAPTAB 4 + TRAPTAB 5 + + /* struct tricore_trap_s: taddr at 0, tid at 4, tclass at 5, tcpu at 6 */ + + .macro TRAPENTRY name, handler + .type \name, %function +\name: + sub.a %sp, 8 + st.a [%sp]0, %a11 + st.b [%sp]4, %d15 + st.b [%sp]5, %d5 + mfcr %d4, TRICORE_CPU_CORE_ID + and %d4, %d4, 7 + st.b [%sp]6, %d4 + mov.aa %a4, %sp + movh.a %a2, hi:\handler + lea %a2, [%a2]lo:\handler + jli %a2 + lea %sp, [%sp]8 + rslcx + rfe + .endm + + .text + .p2align 1 + + TRAPENTRY tricore_trap_entry, tricore_trapcall + TRAPENTRY tricore_syscall_entry, tricore_svcall diff --git a/arch/tricore/src/common/tasking/tricore_vectors.asm b/arch/tricore/src/common/tasking/tricore_vectors.asm new file mode 100644 index 00000000000..0609fd2891a --- /dev/null +++ b/arch/tricore/src/common/tasking/tricore_vectors.asm @@ -0,0 +1,89 @@ +;**************************************************************************** +; arch/tricore/src/common/tasking/tricore_vectors.asm +; +; SPDX-License-Identifier: Apache-2.0 +; +; Licensed to the Apache Software Foundation (ASF) under one or more +; contributor license agreements. See the NOTICE file distributed with +; this work for additional information regarding copyright ownership. The +; ASF licenses this file to you under the Apache License, Version 2.0 (the +; "License"); you may not use this file except in compliance with the +; License. You may obtain a copy of the License at +; +; http://www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +; License for the specific language governing permissions and limitations +; under the License. +; +;**************************************************************************** +; +; TASKING (astc) version of gnu/tricore_vectors.S, same code and layout; see +; there for the description. astc does not run the C preprocessor, so the +; CORE_ID offset (TRICORE_CPU_CORE_ID in arch/csfr.h) is written out. The +; tables are protected, as nothing references them by symbol. +; +;**************************************************************************** + + .extern tricore_trapcall + .extern tricore_svcall + +TRAPSLOT .macro cls, entry + svlcx + mov d5, #cls + j entry + .align 32 + .endm + +TRAPTAB .macro cpu, label + .sdecl ".text.traptab_cpu\cpu",code,protect + .sect ".text.traptab_cpu\cpu" + .align 256 + .global label +label: + TRAPSLOT 0, tricore_trap_entry + TRAPSLOT 1, tricore_trap_entry + TRAPSLOT 2, tricore_trap_entry + TRAPSLOT 3, tricore_trap_entry + TRAPSLOT 4, tricore_trap_entry + TRAPSLOT 5, tricore_trap_entry + TRAPSLOT 6, tricore_syscall_entry + TRAPSLOT 7, tricore_trap_entry + .endm + + TRAPTAB 0, tricore_trap_vectors_cpu0 + TRAPTAB 1, tricore_trap_vectors_cpu1 + TRAPTAB 2, tricore_trap_vectors_cpu2 + TRAPTAB 3, tricore_trap_vectors_cpu3 + TRAPTAB 4, tricore_trap_vectors_cpu4 + TRAPTAB 5, tricore_trap_vectors_cpu5 + +; struct tricore_trap_s: taddr at 0, tid at 4, tclass at 5, tcpu at 6 + +TRAPENTRY .macro name, handler +name: + sub.a sp, #8 + st.a [sp]0, a11 + st.b [sp]4, d15 + st.b [sp]5, d5 + mfcr d4, #0xfe1c ; TRICORE_CPU_CORE_ID + and d4, d4, #7 + st.b [sp]6, d4 + mov.aa a4, sp + movh.a a2, #@HIS(handler) + lea a2, [a2]@LOS(handler) + jli a2 + lea sp, [sp]8 + rslcx + rfe + .endm + + .sdecl ".text.tricore_trap_entry",code + .sect ".text.tricore_trap_entry" + + TRAPENTRY tricore_trap_entry, tricore_trapcall + TRAPENTRY tricore_syscall_entry, tricore_svcall + + .end diff --git a/arch/tricore/src/common/tricore_internal.h b/arch/tricore/src/common/tricore_internal.h index c16c3572bf2..a3b077edfc4 100644 --- a/arch/tricore/src/common/tricore_internal.h +++ b/arch/tricore/src/common/tricore_internal.h @@ -129,6 +129,19 @@ typedef void (*up_vector_t)(void); */ typedef int (*tricore_bustrap_hook_t)(uint32_t tid, void *context); + +/* Trap information that tricore_vectors.S/.asm builds on the stack and + * passes to tricore_trapcall and tricore_svcall; keep the layout in + * sync with the vectors. + */ + +struct tricore_trap_s +{ + uintptr_t taddr; /* Trap return address (A11) */ + uint8_t tid; /* Trap identification number (TIN) */ + uint8_t tclass; /* Trap class */ + uint8_t tcpu; /* Core that took the trap */ +}; #endif /**************************************************************************** diff --git a/arch/tricore/src/common/tricore_trapcall.c b/arch/tricore/src/common/tricore_trapcall.c index 7b0b148c4ad..d86023dccac 100644 --- a/arch/tricore/src/common/tricore_trapcall.c +++ b/arch/tricore/src/common/tricore_trapcall.c @@ -52,7 +52,7 @@ * Private Data ****************************************************************************/ -static IfxCpu_Trap g_trapinfo; +static struct tricore_trap_s g_trapinfo; /* Bus trap hook for safety test modules (e.g., BusMonTst). */ @@ -64,12 +64,7 @@ static tricore_bustrap_hook_t g_bustrap_hook; static void tricore_trapinfo(volatile void *trap) { - IfxCpu_Trap *ctrap = (IfxCpu_Trap *)trap; - - g_trapinfo.tCpu = ctrap->tCpu; - g_trapinfo.tClass = ctrap->tClass; - g_trapinfo.tId = ctrap->tId; - g_trapinfo.tAddr = ctrap->tAddr; + g_trapinfo = *(struct tricore_trap_s *)trap; } /**************************************************************************** @@ -384,9 +379,9 @@ void tricore_trapcall(volatile void *trap) uintptr_t *regs; bool was_interrupt_context; - IfxCpu_Trap *ctrap = (IfxCpu_Trap *)trap; - IfxCpu_Trap_Class tclass = (IfxCpu_Trap_Class)ctrap->tClass; - unsigned int tid = ctrap->tId; + struct tricore_trap_s *ctrap = (struct tricore_trap_s *)trap; + IfxCpu_Trap_Class tclass = (IfxCpu_Trap_Class)ctrap->tclass; + unsigned int tid = ctrap->tid; tricore_trapinfo(trap); diff --git a/arch/tricore/src/tc3xx/CMakeLists.txt b/arch/tricore/src/tc3xx/CMakeLists.txt index 8e801156c1b..539aa84643f 100644 --- a/arch/tricore/src/tc3xx/CMakeLists.txt +++ b/arch/tricore/src/tc3xx/CMakeLists.txt @@ -119,7 +119,6 @@ set(SDK_CSRCS "${CONFIG_DIR}/Ifx_Cfg_Ssw.c" "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Asclin/Std/IfxAsclin.c" "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Cpu/Std/IfxCpu.c" - "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/Cpu/Trap/IfxCpu_Trap.c" "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/_Impl/IfxAsclin_cfg.c" "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/_Impl/IfxCpu_cfg.c" "${ILLD_DIR}/Libraries/iLLD/TC3xx/Tricore/_Impl/IfxStm_cfg.c" diff --git a/arch/tricore/src/tc3xx/Make.defs b/arch/tricore/src/tc3xx/Make.defs index d9c01c308de..3db2e310871 100644 --- a/arch/tricore/src/tc3xx/Make.defs +++ b/arch/tricore/src/tc3xx/Make.defs @@ -95,7 +95,6 @@ SDK_INCDIR += $(ILLD_DIR)/Libraries/Service/CpuGeneric SDK_CSRCS += ${CONFIG_DIR}/Ifx_Cfg_Ssw.c SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Asclin/Std/IfxAsclin.c SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Cpu/Std/IfxCpu.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/Cpu/Trap/IfxCpu_Trap.c SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/_Impl/IfxAsclin_cfg.c SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/_Impl/IfxCpu_cfg.c SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC3xx/Tricore/_Impl/IfxStm_cfg.c diff --git a/arch/tricore/src/tc4xx/CMakeLists.txt b/arch/tricore/src/tc4xx/CMakeLists.txt index 1bb22656604..d849f243f2c 100644 --- a/arch/tricore/src/tc4xx/CMakeLists.txt +++ b/arch/tricore/src/tc4xx/CMakeLists.txt @@ -158,7 +158,6 @@ set(SDK_CSRCS "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/_Impl/IfxCpu_cfg.c" "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/_Impl/IfxStm_cfg.c" "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Cpu/Std/IfxCpu.c" - "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Cpu/Trap/IfxCpu_Trap.c" "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Scu/Std/IfxScuEru.c" "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Stm/Std/IfxStm.c" "${ILLD_DIR}/Libraries/iLLD/TC4xx/Tricore/Smm/Std/IfxSmm.c" diff --git a/arch/tricore/src/tc4xx/Make.defs b/arch/tricore/src/tc4xx/Make.defs index 10f0f47059d..bbc3a15fa28 100644 --- a/arch/tricore/src/tc4xx/Make.defs +++ b/arch/tricore/src/tc4xx/Make.defs @@ -135,7 +135,6 @@ SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/CpuGeneric/Src/Std/IfxSrc.c SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/_Impl/IfxCpu_cfg.c SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/_Impl/IfxStm_cfg.c SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Cpu/Std/IfxCpu.c -SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Cpu/Trap/IfxCpu_Trap.c SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Scu/Std/IfxScuEru.c SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Stm/Std/IfxStm.c SDK_CSRCS += $(ILLD_DIR)/Libraries/iLLD/TC4xx/Tricore/Smm/Std/IfxSmm.c
