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commit e59a9eb994d7eb4083ef1dfd3c2f50a6c56394b1 Author: raiden00pl <[email protected]> AuthorDate: Mon Nov 9 08:32:28 2026 +0100 arch/arm/stm32n6: Wait for the whole clock switch status. The final wait of the clock configuration only checked that the bits of the requested selection were set in SWS. For a switch to HSI, MSI or HSE it returned at once, before the switch was done. Compare the whole CPUSWS and SYSSWS fields instead. Assisted-by: Claude:claude-fable-5-1 Signed-off-by: raiden00pl <[email protected]> --- arch/arm/src/stm32n6/stm32n6xx_rcc.c | 30 +++++++++++++++++++++++++++--- 1 file changed, 27 insertions(+), 3 deletions(-) diff --git a/arch/arm/src/stm32n6/stm32n6xx_rcc.c b/arch/arm/src/stm32n6/stm32n6xx_rcc.c index 9e6c85d8b86..c76ba39ff02 100644 --- a/arch/arm/src/stm32n6/stm32n6xx_rcc.c +++ b/arch/arm/src/stm32n6/stm32n6xx_rcc.c @@ -236,6 +236,30 @@ static bool rcc_waitflag(uint32_t addr, uint32_t mask, bool set) return false; } +/**************************************************************************** + * Name: rcc_waitfield + * + * Description: + * Spin until the bits in mask of the register at addr equal value. + * Returns false on timeout. + * + ****************************************************************************/ + +static bool rcc_waitfield(uint32_t addr, uint32_t mask, uint32_t value) +{ + volatile int32_t timeout; + + for (timeout = CLKRDY_TIMEOUT; timeout > 0; timeout--) + { + if ((getreg32(addr) & mask) == value) + { + return true; + } + } + + return false; +} + /**************************************************************************** * Name: rcc_enableahb1 * @@ -876,7 +900,7 @@ void stm32_stdclockconfig(void) putreg32(RCC_MEMENR_ALLAXISRAM | RCC_MEMENR_CACHEAXIRAMEN, STM32_RCC_MEMENSR); - rcc_waitflag(STM32_RCC_CFGR1, - RCC_CFGR1_SW2SWS(STM32_RCC_CFGR1_CPUSW | - STM32_RCC_CFGR1_SYSSW), true); + rcc_waitfield(STM32_RCC_CFGR1, RCC_CFGR1_SWS_MASK, + RCC_CFGR1_SW2SWS(STM32_RCC_CFGR1_CPUSW | + STM32_RCC_CFGR1_SYSSW)); }
