hujun260 opened a new pull request, #21751:
URL: https://github.com/apache/nuttx/pull/21751
# NuttX PR Description
## Title
arch/arm64: add TrustZone idle world-switch and secure SGI support
## Description
This PR adds ARM64 TrustZone dual-OS support for cooperative idle-time world
switching between the TEE and REE, together with secure SGI signaling from
the
non-secure world through EL3.
## Changes
### Idle world switching
Add TrustZone-aware idle handling in `arm64_idle.c`:
- When the TEE has no runnable tasks, issue the `NUTTXSPD_TEE_IDLE` SMC to
yield the CPU to the REE.
- When the REE is idle, issue the `NUTTXSPD_REE_IDLE` SMC to yield the CPU
back
to the TEE.
- Allow the TEE and REE to coexist while each world gives up idle CPU time to
the other world.
### Secure SGI signaling
Add `arm64_send_secure_sgi()` in `arm64_gicv3.c`:
- Allow the non-secure world to request a secure SGI through EL3.
- Use the `NUTTXSPD_SEND_SECURE_SGI` SMC interface.
- Deliver the requested interrupt as a Group 1 Secure SGI.
- Enable cross-world interrupt signaling between the REE and TEE.
## Motivation
Support cooperative CPU sharing and interrupt signaling in ARM64 TrustZone
dual-OS deployments. The idle world-switch path allows the inactive OS to
yield
the CPU, while secure SGI forwarding lets the non-secure OS notify the secure
world through the EL3 firmware.
## Runtime Testing
The following runtime log was captured from the Vela QEMU ARM64 TrustZone
environment using the `qemu-arm64-v8a-ap` configuration:
- CPU: Cortex-A53
- SMP: 4 CPUs
- Memory: 1057 MiB
- Shared memory: 4 MiB ivshmem region
- GDB server: TCP port `7775`
### Trusted Firmware-A and BL32 initialization
```text
NOTICE: Booting Trusted Firmware
NOTICE: BL1: v2.14.0(debug):fb1381d84
INFO: BL2: Loading image id 4
INFO: Handoff to BL32
NOTICE: BL31: Initializing runtime services
INFO: NUTTXSPD: BL32 ep=0xe100000
INFO: NUTTXSPD: BL32 CPU0 entry done
INFO: NUTTXSPD: BL32 CPU1 entry done
INFO: NUTTXSPD: BL32 CPU2 entry done
INFO: NUTTXSPD: BL32 CPU3 entry done
INFO: Entry point address = 0x40280000
```
### AP and TEE initialization
```text
0.382308 8 I 0 ap pci_sdhci_probe: SDHCI controller at 10001000 irq=37
0.383143 8 I 0 ap pci_ivshmem_probe: shmem addr=0x8000400000 size=4194304
reg=0x10001100
0.393617 8 I 0 ap board_init_emmc: GPT partitions registered
NuttX 12.7.2 arm64 ap
21 I 0 tee D/TC:0 21 call_initcalls:40 level 1 register_time_source()
21 I 0 tee D/TC:0 21 call_initcalls:40 level 3 tee_cryp_init()
21 I 0 tee D/TC:0 21 call_initcalls:40 level 4 host_fs_init()
21 I 0 tee D/TC:0 21 host_fs_init:162 host fs init success
21 I 0 tee D/TC:0 21 call_initcalls:40 level 6 default_mobj_init()
```
### AP-side `ostest`
```text
qemu-armv8a-ap> ostest
...
user_main: smp call test
cpu_call_test: Call cpu 0, wait
cpu_call_test: Call cpu 1, wait
cpu_call_test: Call cpu 2, wait
cpu_call_test: Call cpu 3, wait
cpu_call_test: Call multi cpu, wait
cpu_call_test: Test success
user_main: Exiting
ostest_main: Exiting with status 0
```
### TEE-side `ostest`
```text
tee> ostest
...
user_main: smp call test
cpu_call_test: Call cpu 0, wait
cpu_call_test: Call cpu 1, wait
cpu_call_test: Call cpu 2, wait
cpu_call_test: Call cpu 3, wait
cpu_call_test: Call multi cpu, wait
cpu_call_test: Test success
user_main: Exiting
ostest_main: Exiting with status 0
```
## Testing Status
- [ ] Compile-tested with secure-world TrustZone configuration
- [ ] Compile-tested with non-secure-world TrustZone configuration
- [x] Runtime-tested on Vela QEMU ARM64 TrustZone
- [x] BL32 initialized on all four CPUs
- [x] AP-side `ostest` completed with status 0
- [x] TEE-side `ostest` completed with status 0
- [ ] Directly verified TEE-to-REE idle SMC switching
- [ ] Directly verified REE-to-TEE idle SMC switching
- [ ] Directly verified secure SGI forwarding through EL3
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