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commit ad916306394059eaec528b352b46843462968bf0 Author: raiden00pl <[email protected]> AuthorDate: Mon Oct 19 14:46:03 2026 +0200 arch/arm/stm32g4: add STM32G491 support Add the STM32G491R chip with the category 4 peripheral set (no HRTIM, ADC4/5, DAC2/4, COMP5-7, OPAMP4/5, I2C4, SPI4, FDCAN3, TIM5, FMC or QUADSPI), its SRAM layout (80 + 16 KB and 16 KB CCM) and the already prepared single bank 2 KB page flash geometry, whose block lacked its #if/#endif. Signed-off-by: raiden00pl <[email protected]> Assisted-by: Claude Code --- arch/arm/include/stm32g4/chip.h | 28 +++++++++++ .../src/common/stm32/hardware/stm32_flash_v1v2.h | 3 +- .../src/common/stm32/stm32_allocateheap_m3m4_v1.c | 4 ++ arch/arm/src/stm32g4/Kconfig | 57 ++++++++++++++++++++++ 4 files changed, 91 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/stm32g4/chip.h b/arch/arm/include/stm32g4/chip.h index f552caac654..8e9e0375772 100644 --- a/arch/arm/include/stm32g4/chip.h +++ b/arch/arm/include/stm32g4/chip.h @@ -184,6 +184,34 @@ # define STM32_NRNG 1 /* Random number generator (RNG) */ # define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ +#elif defined (CONFIG_ARCH_CHIP_STM32G491R) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA + * (1) 32-bit general timer TIM2 with DMA + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* USART1-3 and UART 4-5 */ +# define STM32_NLPUART 1 /* LPUART1 */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* FDCAN1-2 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed + * with LPM and BCD support) */ +# define STM32_NGPIO 52 /* GPIOA-D, F-G */ +# define STM32_NADC 3 /* 12-bit ADC1-3 */ +# define STM32_NDAC 2 /* 12-bit DAC1 and DAC3 */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + #elif defined (CONFIG_ARCH_CHIP_STM32G474C) # define STM32_NFSMC 0 /* FSMC */ # define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_flash_v1v2.h b/arch/arm/src/common/stm32/hardware/stm32_flash_v1v2.h index 3a3a5c796b1..fb9f37c311a 100644 --- a/arch/arm/src/common/stm32/hardware/stm32_flash_v1v2.h +++ b/arch/arm/src/common/stm32/hardware/stm32_flash_v1v2.h @@ -204,13 +204,14 @@ # define STM32_FLASH_SIZE 128 * 4096 # endif # elif defined(CONFIG_STM32_STM32G49XX) -# elif defined(CONFIG_STM32_FLASH_CONFIG_C) +# if defined(CONFIG_STM32_FLASH_CONFIG_C) # define STM32_FLASH_NPAGES 128 # define STM32_FLASH_PAGESIZE 2048 # elif defined(CONFIG_STM32_FLASH_CONFIG_E) # define STM32_FLASH_NPAGES 256 # define STM32_FLASH_PAGESIZE 2048 +# endif # endif /* Define the Valid Configuration the F1 and F3 */ diff --git a/arch/arm/src/common/stm32/stm32_allocateheap_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_allocateheap_m3m4_v1.c index f314532f8a3..afc83338425 100644 --- a/arch/arm/src/common/stm32/stm32_allocateheap_m3m4_v1.c +++ b/arch/arm/src/common/stm32/stm32_allocateheap_m3m4_v1.c @@ -522,6 +522,8 @@ #if defined(CONFIG_STM32_STM32G47XX) # define SRAM1_END 0x20020000 +#elif defined(CONFIG_STM32_STM32G49XX) +# define SRAM1_END 0x20018000 #elif defined(CONFIG_STM32_STM32G43XX) # define SRAM1_END 0x20005800 #else @@ -534,6 +536,8 @@ #if defined(CONFIG_STM32_STM32G47XX) # define SRAM2_END 0x10008000 +#elif defined(CONFIG_STM32_STM32G49XX) +# define SRAM2_END 0x10004000 #elif defined(CONFIG_STM32_STM32G43XX) # define SRAM2_END 0x10002700 #else diff --git a/arch/arm/src/stm32g4/Kconfig b/arch/arm/src/stm32g4/Kconfig index 3c173b1d010..ec6d5b340d6 100644 --- a/arch/arm/src/stm32g4/Kconfig +++ b/arch/arm/src/stm32g4/Kconfig @@ -71,6 +71,13 @@ config ARCH_CHIP_STM32G474V select STM32_STM32G4XXV select STM32_STM32G474V +config ARCH_CHIP_STM32G491R + bool "STM32G491R" + select STM32_STM32G49XX + select STM32_STM32G4XXR + select STM32_STM32G491R + select STM32_HAVE_USBFS + endchoice endif @@ -343,3 +350,53 @@ config STM32_STM32G474V select STM32_HAVE_SPI4 select STM32_HAVE_UART4 select STM32_HAVE_UART5 + +config STM32_STM32G49XX + bool + default n + select STM32_STM32G4XXX + select STM32_STM32G4_CAT4 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_CCM + select STM32_HAVE_COMP1 + select STM32_HAVE_COMP2 + select STM32_HAVE_COMP3 + select STM32_HAVE_COMP4 + select STM32_HAVE_CORDIC + select STM32_HAVE_CRS + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC3 + select STM32_HAVE_FMAC + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_I2S3 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPUART1 + select STM32_HAVE_OPAMP1 + select STM32_HAVE_OPAMP2 + select STM32_HAVE_OPAMP3 + select STM32_HAVE_OPAMP6 + select STM32_HAVE_RNG + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM20 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM8 + select STM32_HAVE_USART3 + select STM32_HAVE_UCPD + select STM32_HAVE_USBDEV + +config STM32_STM32G491R + bool + default n + select STM32_HAVE_UART4 + select STM32_HAVE_UART5
