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commit 33901969fea2903c4213d6e91920bde8ab2832ef Author: raiden00pl <[email protected]> AuthorDate: Sat Oct 10 15:43:46 2020 +0200 Fix nxstyle warnings --- arch/arm/include/stm32f0l0g0/stm32l0_irq.h | 4 +- arch/arm/src/nrf52/hardware/nrf52_spi.h | 14 ++--- arch/arm/src/nrf52/hardware/nrf52_twi.h | 14 ++--- arch/arm/src/stm32f0l0g0/hardware/stm32_comp.h | 44 +++++++-------- arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h | 17 ++++-- arch/arm/src/stm32f0l0g0/hardware/stm32g0_dmamux.h | 2 +- arch/arm/src/stm32f0l0g0/hardware/stm32g0_exti.h | 28 ++++----- .../src/stm32f0l0g0/hardware/stm32g0_memorymap.h | 3 +- arch/arm/src/stm32f0l0g0/hardware/stm32g0_rcc.h | 48 ++++++++-------- arch/arm/src/stm32f0l0g0/hardware/stm32g0_syscfg.h | 44 +++++++-------- arch/arm/src/stm32f0l0g0/hardware/stm32l0_rcc.h | 66 +++++++++++----------- arch/arm/src/stm32f0l0g0/hardware/stm32l0_syscfg.h | 16 +++--- arch/arm/src/stm32f0l0g0/stm32_adc.h | 56 ++++++++++-------- arch/arm/src/stm32f0l0g0/stm32_lowputc.c | 8 +-- arch/arm/src/stm32f0l0g0/stm32l0_rcc.c | 33 +++++------ .../nrf52/nrf52840-dongle/src/nrf52840-dongle.h | 2 +- .../arm/stm32f0l0g0/b-l072z-lrwan1/include/board.h | 4 +- .../b-l072z-lrwan1/src/b-l072z-lrwan1.h | 6 +- .../stm32f0l0g0/b-l072z-lrwan1/src/stm32_boot.c | 20 +++---- .../stm32f0l0g0/b-l072z-lrwan1/src/stm32_bringup.c | 5 +- .../arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_spi.c | 23 +++++--- .../stm32f0l0g0/nucleo-g071rb/src/nucleo-g071rb.h | 2 +- .../arm/stm32f0l0g0/nucleo-g071rb/src/stm32_boot.c | 17 +++--- .../arm/stm32f0l0g0/nucleo-l073rz/include/board.h | 4 +- .../stm32f0l0g0/nucleo-l073rz/src/nucleo-l073rz.h | 15 +++-- .../arm/stm32f0l0g0/nucleo-l073rz/src/stm32_boot.c | 17 +++--- .../stm32f0l0g0/nucleo-l073rz/src/stm32_bringup.c | 8 ++- .../arm/stm32f0l0g0/nucleo-l073rz/src/stm32_spi.c | 30 ++++++---- .../stm32f0l0g0/nucleo-l073rz/src/stm32_sx127x.c | 3 +- drivers/power/motor.c | 31 ++++++---- drivers/power/powerled.c | 20 ++++--- drivers/power/smps.c | 27 ++++++--- drivers/wireless/lpwan/sx127x/sx127x.h | 51 ++++++++--------- include/nuttx/power/motor.h | 9 ++- include/nuttx/power/powerled.h | 23 ++++---- include/nuttx/power/smps.h | 5 +- include/nuttx/wireless/lpwan/sx127x.h | 2 +- libs/libdsp/lib_foc.c | 4 +- 38 files changed, 394 insertions(+), 331 deletions(-) diff --git a/arch/arm/include/stm32f0l0g0/stm32l0_irq.h b/arch/arm/include/stm32f0l0g0/stm32l0_irq.h index 745ffd2..fba2850 100644 --- a/arch/arm/include/stm32f0l0g0/stm32l0_irq.h +++ b/arch/arm/include/stm32f0l0g0/stm32l0_irq.h @@ -93,7 +93,7 @@ /**************************************************************************************************** * Public Data -****************************************************************************************************/ + ****************************************************************************************************/ #ifndef __ASSEMBLY__ #ifdef __cplusplus @@ -105,7 +105,7 @@ extern "C" #endif /**************************************************************************************************** - * Public Functions + * Public Functions Prototypes ****************************************************************************************************/ #undef EXTERN diff --git a/arch/arm/src/nrf52/hardware/nrf52_spi.h b/arch/arm/src/nrf52/hardware/nrf52_spi.h index 2b051f4..47d7e5d 100644 --- a/arch/arm/src/nrf52/hardware/nrf52_spi.h +++ b/arch/arm/src/nrf52/hardware/nrf52_spi.h @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ***************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_SPI_H #define __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_SPI_H /**************************************************************************** * Included Files - ***************************************************************************/ + ****************************************************************************/ #include <nuttx/config.h> #include "hardware/nrf52_memorymap.h" /**************************************************************************** * Pre-processor Definitions - ***************************************************************************/ + ****************************************************************************/ -/* Register offsets for SPI master (SPIM) **********************************/ +/* Register offsets for SPI master (SPIM) ***********************************/ #define NRF52_SPIM_TASK_START_OFFSET (0x0010) /* Start SPI transaction */ #define NRF52_SPIM_TASK_STOP_OFFSET (0x0014) /* Stop SPI transaction */ @@ -69,7 +69,7 @@ #define NRF52_SPIM_DCXCNT_OFFSET (0x0570) /* DCX configuration */ #define NRF52_SPIM_ORC_OFFSET (0x05c0) /* ORC */ -/* Register offsets for SPI slave (SPIS) ***********************************/ +/* Register offsets for SPI slave (SPIS) ************************************/ #define NRF52_SPIS_SHORTS_OFFSET (0x0200) /* Shortcuts between local events and tasks */ #define NRF52_SPIS_INTENSET_OFFSET (0x0304) /* Enable interrupt */ @@ -93,7 +93,7 @@ #define NRF52_SPIS_DEF_OFFSET (0x055c) /* Default character */ #define NRF52_SPIS_ORC_OFFSET (0x05c0) /* Over-read character */ -/* Register Bitfield Definitions for SPIM **********************************/ +/* Register Bitfield Definitions for SPIM ***********************************/ /* TASKS_START Register */ @@ -235,7 +235,7 @@ #define SPIM_PSELDCX_PORT_MASK (0x1 << SPIM_PSELDCX_PORT_SHIFT) #define SPIM_PSELDCX_CONNECTED (1 << 31) /* Bit 31: Connection */ -/* Register Bitfield Definitions for SPIS *******************************************************/ +/* Register Bitfield Definitions for SPIS ***********************************/ /* TODO */ diff --git a/arch/arm/src/nrf52/hardware/nrf52_twi.h b/arch/arm/src/nrf52/hardware/nrf52_twi.h index 21f7d13..23a122d 100644 --- a/arch/arm/src/nrf52/hardware/nrf52_twi.h +++ b/arch/arm/src/nrf52/hardware/nrf52_twi.h @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ***************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_TWI_H #define __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_TWI_H /**************************************************************************** * Included Files - ***************************************************************************/ + ****************************************************************************/ #include <nuttx/config.h> #include "hardware/nrf52_memorymap.h" /**************************************************************************** * Pre-processor Definitions - ***************************************************************************/ + ****************************************************************************/ -/* Register offsets for TWI master (TWIM) **********************************/ +/* Register offsets for TWI master (TWIM) ***********************************/ #define NRF52_TWIM_TASKS_STARTRX_OFFSET 0x0000 /* Start TWIM receive sequence */ #define NRF52_TWIM_TASKS_STARTTX_OFFSET 0x0008 /* Start TWIM transmit sequence */ @@ -65,7 +65,7 @@ #define NRF52_TWIM_TXLIST_OFFSET 0x0550 /* TX EasyDMA list type */ #define NRF52_TWIM_ADDRESS_OFFSET 0x0588 /* TWIM address */ -/* Register offsets for TWI slave (TWIS) ***********************************/ +/* Register offsets for TWI slave (TWIS) ************************************/ #define NRF52_TWIS_TASKS_STOP_OFFSET 0x0014 /* Stop TWIS transaction */ #define NRF52_TWIS_TASKS_SUSPEND_OFFSET 0x001c /* Suspend TWIS transaction */ @@ -100,7 +100,7 @@ #define NRF52_TWIS_CONFIG_OFFSET 0x0594 /* Configuration register for the address match mechanism */ #define NRF52_TWIS_ORC_OFFSET 0x05c0 /* Over-read character */ -/* Register Bitfield Definitions for TWIM **********************************/ +/* Register Bitfield Definitions for TWIM ***********************************/ /* SHORTS Register */ @@ -181,7 +181,7 @@ #define TWIM_ADDRESS_SHIFT (0) /* Bits 0-6: Address used in the TWI transfer */ #define TWIM_ADDRESS_MASK (0x7f << TWIM_ADDRESS_SHIFT) -/* Register Bitfield Definitions for TWIS *******************************************************/ +/* Register Bitfield Definitions for TWIS ***********************************/ /* TODO */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_comp.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_comp.h index 80ba506..4dbf69f 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_comp.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_comp.h @@ -45,15 +45,15 @@ /* COMP control and status register */ -#define COMP_CSR_COMP1EN (1 << 0) /* Bit 0: Comparator 1 enable */ -#define COMP_CSR_COMP1SW1 (1 << 1) /* Bit 1: Comparator 1 non inverting input DAC switch */ -#define COMP_CSR_COMP1MODE_SHIFT (2) /* Bits 2-3: Compator 1 mode */ +#define COMP_CSR_COMP1EN (1 << 0) /* Bit 0: Comparator 1 enable */ +#define COMP_CSR_COMP1SW1 (1 << 1) /* Bit 1: Comparator 1 non inverting input DAC switch */ +#define COMP_CSR_COMP1MODE_SHIFT (2) /* Bits 2-3: Compator 1 mode */ #define COMP_CSR_COMP1MODE_MASK (3 << COMP_CSR_COMP1MODE_SHIFT) -# define COMP_CSR_COMP1MODE_HIGH (0 << COMP_CSR_COMP1MODE_SHIFT) /* 00: High Speed / full power */ -# define COMP_CSR_COMP1MODE_MEDIUM (1 << COMP_CSR_COMP1MODE_SHIFT) /* 01: Medium Speed / medium power */ -# define COMP_CSR_COMP1MODE_LOW (2 << COMP_CSR_COMP1MODE_SHIFT) /* 10: Low Speed / low-power */ -# define COMP_CSR_COMP1MODE_VLOW (3 << COMP_CSR_COMP1MODE_SHIFT) /* 11: Very-low Speed / ultra-low power */ -#define COMP_CSR_COMP1INSEL_SHIFT (4) /* Bits 4-6: Comparator 1 inverting input selection */ +# define COMP_CSR_COMP1MODE_HIGH (0 << COMP_CSR_COMP1MODE_SHIFT) /* 00: High Speed / full power */ +# define COMP_CSR_COMP1MODE_MEDIUM (1 << COMP_CSR_COMP1MODE_SHIFT) /* 01: Medium Speed / medium power */ +# define COMP_CSR_COMP1MODE_LOW (2 << COMP_CSR_COMP1MODE_SHIFT) /* 10: Low Speed / low-power */ +# define COMP_CSR_COMP1MODE_VLOW (3 << COMP_CSR_COMP1MODE_SHIFT) /* 11: Very-low Speed / ultra-low power */ +#define COMP_CSR_COMP1INSEL_SHIFT (4) /* Bits 4-6: Comparator 1 inverting input selection */ #define COMP_CSR_COMP1INSEL_MASK (7 << COMP_CSR_COMP1INSEL_SHIFT) # define COMP_CSR_COMP1INSEL_1P4VREF (0 << COMP_CSR_COMP1INSEL_SHIFT) /* 000: 1/4 of Vrefint */ # define COMP_CSR_COMP1INSEL_1P2VREF (1 << COMP_CSR_COMP1INSEL_SHIFT) /* 001: 1/2 of Vrefint */ @@ -62,7 +62,7 @@ # define COMP_CSR_COMP1INSEL_INM4 (4 << COMP_CSR_COMP1INSEL_SHIFT) /* 100: COMP1_INM4 (PA4 DAC_OUT1 if enabled) */ # define COMP_CSR_COMP1INSEL_INM5 (5 << COMP_CSR_COMP1INSEL_SHIFT) /* 101: COMP1_INM5 (PA5 DAC_OUT2 if present and enabled) */ # define COMP_CSR_COMP1INSEL_INM6 (6 << COMP_CSR_COMP1INSEL_SHIFT) /* 110: COMP1_INM6 (PA0) */ -#define COMP_CSR_COMP1OUTSEL_SHIFT (8) /* Bits 8-10: Comparator 1 output selection*/ +#define COMP_CSR_COMP1OUTSEL_SHIFT (8) /* Bits 8-10: Comparator 1 output selection*/ #define COMP_CSR_COMP1OUTSEL_MASK (7 << COMP_CSR_COMP1OUTSEL_MASK) # define COMP_CSR_COMP1OUTSEL_NOSEL (0 << COMP_CSR_COMP1OUTSEL_MASK) /* 000: no selection */ # define COMP_CSR_COMP1OUTSEL_T1BRK (1 << COMP_CSR_COMP1OUTSEL_MASK) /* 001: Timer 1 break input */ @@ -72,24 +72,24 @@ # define COMP_CSR_COMP1OUTSEL_T2OCRC (5 << COMP_CSR_COMP1OUTSEL_MASK) /* 101: Timer 2 OCrefclear input */ # define COMP_CSR_COMP1OUTSEL_T3ICAP (6 << COMP_CSR_COMP1OUTSEL_MASK) /* 110: Timer 3 input capture 1 */ # define COMP_CSR_COMP1OUTSEL_T3OCRC (7 << COMP_CSR_COMP1OUTSEL_MASK) /* 111: Timer 3 OCrefclear input */ -#define COMP_CSR_COMP1POL (1 << 11) /* Bit 11: Comparator 1 output polarity */ -#define COMP_CSR_COMP1HYST_SHIFT (12) /* Bits 12-13: Comparator 1 hysteresis */ +#define COMP_CSR_COMP1POL (1 << 11) /* Bit 11: Comparator 1 output polarity */ +#define COMP_CSR_COMP1HYST_SHIFT (12) /* Bits 12-13: Comparator 1 hysteresis */ #define COMP_CSR_COMP1HYST_MASK (3 << COMP_CSR_COMP1HYST_SHIFT) # define COMP_CSR_COMP1HYST_NOHYST (0 << COMP_CSR_COMP1HYST_MASK) /* 00: No hysteresis */ # define COMP_CSR_COMP1HYST_LOWHYST (1 << COMP_CSR_COMP1HYST_MASK) /* 01: Low hysteresis */ # define COMP_CSR_COMP1HYST_MDHYST (2 << COMP_CSR_COMP1HYST_MASK) /* 10: Medium hysteresis */ # define COMP_CSR_COMP1HYST_HIHYST (3 << COMP_CSR_COMP1HYST_MASK) /* 11: Low hysteresis */ -#define COMP_CSR_COMP1OUT (1 << 14) /* Bit 14: Comparator 1 output */ -#define COMP_CSR_COMP1LOCK (1 << 15) /* Bit 15: Comparator 1 lock */ +#define COMP_CSR_COMP1OUT (1 << 14) /* Bit 14: Comparator 1 output */ +#define COMP_CSR_COMP1LOCK (1 << 15) /* Bit 15: Comparator 1 lock */ -#define COMP_CSR_COMP2EN (1 << 16) /* Bit 16: Comparator 2 enable */ -#define COMP_CSR_COMP2MODE_SHIFT (18) /* Bits 18-19: Compator 2 mode */ +#define COMP_CSR_COMP2EN (1 << 16) /* Bit 16: Comparator 2 enable */ +#define COMP_CSR_COMP2MODE_SHIFT (18) /* Bits 18-19: Compator 2 mode */ #define COMP_CSR_COMP2MODE_MASK (3 << COMP_CSR_COMP2MODE_SHIFT) # define COMP_CSR_COMP2MODE_HIGH (0 << COMP_CSR_COMP2MODE_SHIFT) /* 00: High Speed / full power */ # define COMP_CSR_COMP2MODE_MEDIUM (1 << COMP_CSR_COMP2MODE_SHIFT) /* 01: Medium Speed / medium power */ # define COMP_CSR_COMP2MODE_LOW (2 << COMP_CSR_COMP2MODE_SHIFT) /* 10: Low Speed / low-power */ # define COMP_CSR_COMP2MODE_VLOW (3 << COMP_CSR_COMP2MODE_SHIFT) /* 11: Very-low Speed / ultra-low power */ -#define COMP_CSR_COMP2INSEL_SHIFT (20) /* Bits 20-22: Comparator 2 inverting input selection */ +#define COMP_CSR_COMP2INSEL_SHIFT (20) /* Bits 20-22: Comparator 2 inverting input selection */ #define COMP_CSR_COMP2INSEL_MASK (7 << COMP_CSR_COMP2INSEL_SHIFT) # define COMP_CSR_COMP2INSEL_1P4VREF (0 << COMP_CSR_COMP2INSEL_SHIFT) /* 000: 1/4 of Vrefint */ # define COMP_CSR_COMP2INSEL_1P2VREF (1 << COMP_CSR_COMP2INSEL_SHIFT) /* 001: 1/2 of Vrefint */ @@ -98,8 +98,8 @@ # define COMP_CSR_COMP2INSEL_INM4 (4 << COMP_CSR_COMP2INSEL_SHIFT) /* 100: COMP1_INM4 (PA4 DAC_OUT1 if enabled) */ # define COMP_CSR_COMP2INSEL_INM5 (5 << COMP_CSR_COMP2INSEL_SHIFT) /* 101: COMP1_INM5 (PA5 DAC_OUT2 if present and enabled) */ # define COMP_CSR_COMP2INSEL_INM6 (6 << COMP_CSR_COMP2INSEL_SHIFT) /* 110: COMP1_INM6 (PA2) */ -#define COMP_CSR_WNDWEN (1 << 23) /* Bit 23: Window mode enable */ -#define COMP_CSR_COMP2OUTSEL_SHIFT (24) /* Bits 24-26: Comparator 1 output selection*/ +#define COMP_CSR_WNDWEN (1 << 23) /* Bit 23: Window mode enable */ +#define COMP_CSR_COMP2OUTSEL_SHIFT (24) /* Bits 24-26: Comparator 1 output selection*/ #define COMP_CSR_COMP2OUTSEL_MASK (7 << COMP_CSR_COMP2OUTSEL_MASK) # define COMP_CSR_COMP2OUTSEL_NOSEL (0 << COMP_CSR_COMP2OUTSEL_MASK) /* 000: no selection */ # define COMP_CSR_COMP2OUTSEL_T1BRK (1 << COMP_CSR_COMP2OUTSEL_MASK) /* 001: Timer 1 break input */ @@ -109,14 +109,14 @@ # define COMP_CSR_COMP2OUTSEL_T2OCRC (5 << COMP_CSR_COMP2OUTSEL_MASK) /* 101: Timer 2 OCrefclear input */ # define COMP_CSR_COMP2OUTSEL_T3ICAP (6 << COMP_CSR_COMP2OUTSEL_MASK) /* 110: Timer 3 input capture 1 */ # define COMP_CSR_COMP2OUTSEL_T3OCRC (7 << COMP_CSR_COMP2OUTSEL_MASK) /* 111: Timer 3 OCrefclear input */ -#define COMP_CSR_COMP2POL (1 << 27) /* Bit 27: Comparator 2 output polarity */ -#define COMP_CSR_COMP2HYST_SHIFT (12) /* Bits 12-13: Comparator 1 hysteresis */ +#define COMP_CSR_COMP2POL (1 << 27) /* Bit 27: Comparator 2 output polarity */ +#define COMP_CSR_COMP2HYST_SHIFT (12) /* Bits 12-13: Comparator 1 hysteresis */ #define COMP_CSR_COMP2HYST_MASK (3 << COMP_CSR_COMP2HYST_SHIFT) # define COMP_CSR_COMP2HYST_NOHYST (0 << COMP_CSR_COMP2HYST_MASK) /* 00: No hysteresis */ # define COMP_CSR_COMP2HYST_LOWHYST (1 << COMP_CSR_COMP2HYST_MASK) /* 01: Low hysteresis */ # define COMP_CSR_COMP2HYST_MDHYST (2 << COMP_CSR_COMP2HYST_MASK) /* 10: Medium hysteresis */ # define COMP_CSR_COMP2HYST_HIHYST (3 << COMP_CSR_COMP2HYST_MASK) /* 11: Low hysteresis */ -#define COMP_CSR_COMP2OUT (1 << 14) /* Bit 14: Comparator 1 output */ -#define COMP_CSR_COMP2LOCK (1 << 15) /* Bit 15: Comparator 1 lock */ +#define COMP_CSR_COMP2OUT (1 << 14) /* Bit 14: Comparator 1 output */ +#define COMP_CSR_COMP2LOCK (1 << 15) /* Bit 15: Comparator 1 lock */ #endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_COMP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h index b0bf417..5add3ac 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h @@ -44,10 +44,10 @@ #define STM32_DMAMUX_C4CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(4) #define STM32_DMAMUX_C5CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(5) #define STM32_DMAMUX_C6CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(6) - /* 0x01C-0x07C: Reserved */ -#define STM32_DMAMUX_CSR_OFFSET 0x0080 /* DMAMUX12 request line multiplexer interrupt channel status register */ -#define STM32_DMAMUX_CFR_OFFSET 0x0084 /* DMAMUX12 request line multiplexer interrupt clear flag register */ - /* 0x088-0x0FC: Reserved */ + /* 0x01C-0x07C: Reserved */ +#define STM32_DMAMUX_CSR_OFFSET 0x0080 /* DMAMUX12 request line multiplexer interrupt channel status register */ +#define STM32_DMAMUX_CFR_OFFSET 0x0084 /* DMAMUX12 request line multiplexer interrupt clear flag register */ + /* 0x088-0x0FC: Reserved */ #define STM32_DMAMUX_RGXCR_OFFSET(x) (0x0100+0x004*(x)) /* DMAMUX12 request generator channel x configuration register */ #define STM32_DMAMUX_RG0CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(0) #define STM32_DMAMUX_RG1CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(1) @@ -106,8 +106,9 @@ /* DMAMUX12 request generator channel x configuration register */ -#define DMAMUX_RGCR_SIGID_SHIFT (0) /* Bits 0-4: Signal identifiaction */ - /* WARNING: different length for DMAMUX1 and DMAMUX2 !*/ +#define DMAMUX_RGCR_SIGID_SHIFT (0) /* Bits 0-4: Signal identifiaction + * WARNING: different length for DMAMUX1 and DMAMUX2 ! + */ #define DMAMUX_RGCR_SIGID_MASK (0x1f << DMAMUX_RGCR_SIGID_SHIFT) #define DMAMUX_RGCR_OIE (8) /* Bit 8: Trigger overrun interrupt enable */ #define DMAMUX_RGCR_GE (16) /* Bit 16: DMA request generator channel X enable*/ @@ -136,6 +137,10 @@ #define DMAMAP_CONTROLLER(m) ((m) >> 8 & 0x07) #define DMAMAP_REQUEST(m) ((m) >> 0 & 0xff) +/************************************************************************************ + * Included Files + ************************************************************************************/ + /* Import DMAMUX map */ #if defined(CONFIG_STM32F0L0G0_STM32G0) diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_dmamux.h b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_dmamux.h index 92f58d1..0484b7f 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_dmamux.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_dmamux.h @@ -32,7 +32,7 @@ * Pre-processor Definitions ************************************************************************************/ -/* DMAMUX1 mapping ****************************************************/ +/* DMAMUX1 mapping ******************************************************************/ /* NOTE: DMAMUX1 channels 0 to 7 are connected to DMA1 channels 0 to 7 */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_exti.h b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_exti.h index bc95b07..3da1930 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_exti.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_exti.h @@ -39,21 +39,21 @@ /* Register Offsets *****************************************************************/ -#define STM32_EXTI_RTSR1_OFFSET 0x0000 /* Rising Trigger selection register 1 */ -#define STM32_EXTI_FTSR1_OFFSET 0x0004 /* Falling Trigger selection register 1 */ -#define STM32_EXTI_SWIER1_OFFSET 0x0008 /* Software interrupt event register 1 */ -#define STM32_EXTI_RPR1_OFFSET 0x000c /* Rising edge pending register 1 */ -#define STM32_EXTI_FPR1_OFFSET 0x0010 /* Falling edge pending register 1 */ +#define STM32_EXTI_RTSR1_OFFSET 0x0000 /* Rising Trigger selection register 1 */ +#define STM32_EXTI_FTSR1_OFFSET 0x0004 /* Falling Trigger selection register 1 */ +#define STM32_EXTI_SWIER1_OFFSET 0x0008 /* Software interrupt event register 1 */ +#define STM32_EXTI_RPR1_OFFSET 0x000c /* Rising edge pending register 1 */ +#define STM32_EXTI_FPR1_OFFSET 0x0010 /* Falling edge pending register 1 */ #define STM32_EXTI_EXTICR_OFFSET(p) (0x0060 + ((p) & 0x000c)) /* Registers are displaced by 4! */ -#define STM32_EXTI_EXTICR1_OFFSET 0x0060 /* External interrupt selection register 1 */ -#define STM32_EXTI_EXTICR2_OFFSET 0x0064 /* External interrupt selection register 2 */ -#define STM32_EXTI_EXTICR3_OFFSET 0x0068 /* External interrupt selection register 3 */ -#define STM32_EXTI_EXTICR4_OFFSET 0x006c /* External interrupt selection register 4 */ -#define STM32_EXTI_IMR1_OFFSET 0x0080 /* CPU wakeup with interrupt mask register 1 */ -#define STM32_EXTI_EMR1_OFFSET 0x0084 /* CPU wakeup with event mask register 1 */ -#define STM32_EXTI_IMR2_OFFSET 0x0090 /* CPU wakeup with interrupt mask register 2 */ -#define STM32_EXTI_EMR2_OFFSET 0x0094 /* CPU wakeup with event mask register 2 */ +#define STM32_EXTI_EXTICR1_OFFSET 0x0060 /* External interrupt selection register 1 */ +#define STM32_EXTI_EXTICR2_OFFSET 0x0064 /* External interrupt selection register 2 */ +#define STM32_EXTI_EXTICR3_OFFSET 0x0068 /* External interrupt selection register 3 */ +#define STM32_EXTI_EXTICR4_OFFSET 0x006c /* External interrupt selection register 4 */ +#define STM32_EXTI_IMR1_OFFSET 0x0080 /* CPU wakeup with interrupt mask register 1 */ +#define STM32_EXTI_EMR1_OFFSET 0x0084 /* CPU wakeup with event mask register 1 */ +#define STM32_EXTI_IMR2_OFFSET 0x0090 /* CPU wakeup with interrupt mask register 2 */ +#define STM32_EXTI_EMR2_OFFSET 0x0094 /* CPU wakeup with event mask register 2 */ /* Register Addresses ***************************************************************/ @@ -76,7 +76,7 @@ #define EXTI_EXTICR_PORTB (1) /* 0001: PB[x] pin */ #define EXTI_EXTICR_PORTC (2) /* 0010: PC[x] pin */ #define EXTI_EXTICR_PORTD (3) /* 0011: PD[x] pin */ - /* 0100: Reserved */ + /* 0100: Reserved */ #define EXTI_EXTICR_PORTF (5) /* 0100: PF[x] pin */ #define EXTI_EXTICR_PORT_MASK (0xff) diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h index c140c37..f6f94afb 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h @@ -85,7 +85,7 @@ /* APB2 Base Addresses **************************************************************/ #define STM32_SYSCFG_BASE 0x40010000 /* 0x40010000-0x400103ff SYSCFG */ -/* EXTI ??? */ + /* EXTI ??? */ #define STM32_ADC1_BASE 0x40012400 /* 0x40012400-0x400127ff ADC 1 */ #define STM32_TIM1_BASE 0x40012c00 /* 0x40012c00-0x40012fff TIM1 */ #define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff SPI1 */ @@ -115,6 +115,7 @@ #define STM32_GPIOF_BASE 0x50001400 /* 0x50001400-0x500017ff: GPIO Port F */ /* Cortex-M4 Base Addresses *********************************************************/ + /* Other registers -- see armv7-m/nvic.h for standard Cortex-M4 registers in this * address range */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_rcc.h b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_rcc.h index 2c4f95f..1e83d3a 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_rcc.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_rcc.h @@ -107,74 +107,74 @@ /* Clock configuration register */ -#define RCC_CFGR_SW_SHIFT (0) /* Bits 0-2: System clock Switch */ +#define RCC_CFGR_SW_SHIFT (0) /* Bits 0-2: System clock Switch */ #define RCC_CFGR_SW_MASK (7 << RCC_CFGR_SW_SHIFT) # define RCC_CFGR_SW_HSI (0 << RCC_CFGR_SW_SHIFT) /* 000: HSI selected as system clock */ # define RCC_CFGR_SW_HSE (1 << RCC_CFGR_SW_SHIFT) /* 001: HSE selected as system clock */ # define RCC_CFGR_SW_PLL (2 << RCC_CFGR_SW_SHIFT) /* 010: PLL selected as system clock */ # define RCC_CFGR_SW_LSI (3 << RCC_CFGR_SW_SHIFT) /* 011: LSI selected as system clock */ # define RCC_CFGR_SW_LSE (4 << RCC_CFGR_SW_SHIFT) /* 100: LSE selected as system clock */ -#define RCC_CFGR_SWS_SHIFT (3) /* Bits 3-5: System Clock Switch Status */ +#define RCC_CFGR_SWS_SHIFT (3) /* Bits 3-5: System Clock Switch Status */ #define RCC_CFGR_SWS_MASK (3 << RCC_CFGR_SWS_SHIFT) # define RCC_CFGR_SWS_HSI (0 << RCC_CFGR_SWS_SHIFT) /* 000: HSI oscillator used as system clock */ # define RCC_CFGR_SWS_HSE (1 << RCC_CFGR_SWS_SHIFT) /* 001: HSE oscillator used as system clock */ # define RCC_CFGR_SWS_PLL (2 << RCC_CFGR_SWS_SHIFT) /* 010: PLL oscillator used as system clock */ # define RCC_CFGR_SWS_LSI (3 << RCC_CFGR_SWS_SHIFT) /* 011: LSI used as system clock */ # define RCC_CFGR_SWS_LSE (4 << RCC_CFGR_SWS_SHIFT) /* 100: LSE used as system clock */ -#define RCC_CFGR_HPRE_SHIFT (8) /* Bits 8-11: AHB prescaler */ +#define RCC_CFGR_HPRE_SHIFT (8) /* Bits 8-11: AHB prescaler */ #define RCC_CFGR_HPRE_MASK (0x0f << RCC_CFGR_HPRE_SHIFT) -# define RCC_CFGR_HPRE_SYSCLK (0 << RCC_CFGR_HPRE_SHIFT) /* 0xxx: SYSCLK not divided */ -# define RCC_CFGR_HPRE_SYSCLKd2 (8 << RCC_CFGR_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */ -# define RCC_CFGR_HPRE_SYSCLKd4 (9 << RCC_CFGR_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */ +# define RCC_CFGR_HPRE_SYSCLK (0 << RCC_CFGR_HPRE_SHIFT) /* 0xxx: SYSCLK not divided */ +# define RCC_CFGR_HPRE_SYSCLKd2 (8 << RCC_CFGR_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */ +# define RCC_CFGR_HPRE_SYSCLKd4 (9 << RCC_CFGR_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */ # define RCC_CFGR_HPRE_SYSCLKd8 (10 << RCC_CFGR_HPRE_SHIFT) /* 1010: SYSCLK divided by 8 */ # define RCC_CFGR_HPRE_SYSCLKd16 (11 << RCC_CFGR_HPRE_SHIFT) /* 1011: SYSCLK divided by 16 */ # define RCC_CFGR_HPRE_SYSCLKd64 (12 << RCC_CFGR_HPRE_SHIFT) /* 1100: SYSCLK divided by 64 */ # define RCC_CFGR_HPRE_SYSCLKd128 (13 << RCC_CFGR_HPRE_SHIFT) /* 1101: SYSCLK divided by 128 */ # define RCC_CFGR_HPRE_SYSCLKd256 (14 << RCC_CFGR_HPRE_SHIFT) /* 1110: SYSCLK divided by 256 */ # define RCC_CFGR_HPRE_SYSCLKd512 (15 << RCC_CFGR_HPRE_SHIFT) /* 1111: SYSCLK divided by 512 */ -#define RCC_CFGR_PPRE1_SHIFT (12) /* Bits 12-14: APB Low speed prescaler (APB1) */ +#define RCC_CFGR_PPRE1_SHIFT (12) /* Bits 12-14: APB Low speed prescaler (APB1) */ #define RCC_CFGR_PPRE1_MASK (7 << RCC_CFGR_PPRE1_SHIFT) # define RCC_CFGR_PPRE1_HCLK (0 << RCC_CFGR_PPRE1_SHIFT) /* 0xx: HCLK not divided */ # define RCC_CFGR_PPRE1_HCLKd2 (4 << RCC_CFGR_PPRE1_SHIFT) /* 100: HCLK divided by 2 */ # define RCC_CFGR_PPRE1_HCLKd4 (5 << RCC_CFGR_PPRE1_SHIFT) /* 101: HCLK divided by 4 */ # define RCC_CFGR_PPRE1_HCLKd8 (6 << RCC_CFGR_PPRE1_SHIFT) /* 110: HCLK divided by 8 */ # define RCC_CFGR_PPRE1_HCLKd16 (7 << RCC_CFGR_PPRE1_SHIFT) /* 111: HCLK divided by 16 */ - /* Bits 15-23: Reserved */ -#define RCC_CFGR_MCOSEL_SHIFT (24) /* Bits 24-26: Microcontroller clock output selection */ + /* Bits 15-23: Reserved */ +#define RCC_CFGR_MCOSEL_SHIFT (24) /* Bits 24-26: Microcontroller clock output selection */ #define RCC_CFGR_MCOSEL_MASK (7 << RCC_CFGR_MCOSEL_SHIFT) - /* Bit 27: Reserved */ -#define RCC_CFGR_MCOPRE_SHIFT (28) /* Bits 28-30: Microcontroller clock output selection */ + /* Bit 27: Reserved */ +#define RCC_CFGR_MCOPRE_SHIFT (28) /* Bits 28-30: Microcontroller clock output selection */ #define RCC_CFGR_MCOPRE_MASK (7 << RCC_CFGR_MCOPRE_SHIFT) #define RCC_CFGR_RESET 0x00000000 /* PLL clock configuration register */ -#define RCC_PLLCFG_PLLSRC_SHIFT (0) /* Bits 0-1: PLL entry clock source */ +#define RCC_PLLCFG_PLLSRC_SHIFT (0) /* Bits 0-1: PLL entry clock source */ #define RCC_PLLCFG_PLLSRC_MASK (3 << RCC_PLLCFG_PLLSRC_SHIFT) # define RCC_PLLCFG_PLLSRC_NOCLK (0 << RCC_PLLCFG_PLLSRC_SHIFT) # define RCC_PLLCFG_PLLSRC_HSI (2 << RCC_PLLCFG_PLLSRC_SHIFT) # define RCC_PLLCFG_PLLSRC_HSE (3 << RCC_PLLCFG_PLLSRC_SHIFT) - /* Bits 2-3: Reserved */ -#define RCC_PLLCFG_PLLM_SHIFT (4) /* Bits 4-6: Division factor M of the PLL input clock divider */ + /* Bits 2-3: Reserved */ +#define RCC_PLLCFG_PLLM_SHIFT (4) /* Bits 4-6: Division factor M of the PLL input clock divider */ #define RCC_PLLCFG_PLLM_MASK (7 << RCC_PLLCFG_PLLM_SHIFT) #define RCC_PLLCFG_PLLM(n) ((n-1) << RCC_PLLCFG_PLLM_SHIFT) - /* Bit 7: Reserved */ -#define RCC_PLLCFG_PLLN_SHIFT (8) /* Bits 8-14: PLL frequency multiplication factor N */ + /* Bit 7: Reserved */ +#define RCC_PLLCFG_PLLN_SHIFT (8) /* Bits 8-14: PLL frequency multiplication factor N */ #define RCC_PLLCFG_PLLN_MASK (0x7f << RCC_PLLCFG_PLLN_SHIFT) #define RCC_PLLCFG_PLLN(n) ((n) << RCC_PLLCFG_PLLN_SHIFT) - /* Bit 15: Reserved */ -#define RCC_PLLCFG_PLLPEN (1 << 16) /* Bit 16: PLLPCLK clock output enable */ -#define RCC_PLLCFG_PLLP_SHIFT (17) /* Bits 17-21: PLL VCO division factor P for PLLPCLK clock output */ + /* Bit 15: Reserved */ +#define RCC_PLLCFG_PLLPEN (1 << 16) /* Bit 16: PLLPCLK clock output enable */ +#define RCC_PLLCFG_PLLP_SHIFT (17) /* Bits 17-21: PLL VCO division factor P for PLLPCLK clock output */ #define RCC_PLLCFG_PLLP_MASK (0x1f << RCC_PLLCFG_PLLP_SHIFT) #define RCC_PLLCFG_PLLP(n) ((n-1) << RCC_PLLCFG_PLLP_SHIFT) /* n=2,...,32 */ - /* Bits 22-23: Reserved */ -#define RCC_PLLCFG_PLLQEN (1 << 24) /* Bit 24: PLLQCLK clock output enable */ -#define RCC_PLLCFG_PLLQ_SHIFT (25) /* Bits 25-27: Division factor Q of the PLL input clock divider */ + /* Bits 22-23: Reserved */ +#define RCC_PLLCFG_PLLQEN (1 << 24) /* Bit 24: PLLQCLK clock output enable */ +#define RCC_PLLCFG_PLLQ_SHIFT (25) /* Bits 25-27: Division factor Q of the PLL input clock divider */ #define RCC_PLLCFG_PLLQ_MASK (7 << RCC_PLLCFG_PLLQ_SHIFT) #define RCC_PLLCFG_PLLQ(n) ((n-1) << RCC_PLLCFG_PLLQ_SHIFT) -#define RCC_PLLCFG_PLLREN (1 << 28) /* Bit 28: PLLRCLK clock output enable */ -#define RCC_PLLCFG_PLLR_SHIFT (29) /* Bits 29-31: Division factor R of the PLL input clock divider */ +#define RCC_PLLCFG_PLLREN (1 << 28) /* Bit 28: PLLRCLK clock output enable */ +#define RCC_PLLCFG_PLLR_SHIFT (29) /* Bits 29-31: Division factor R of the PLL input clock divider */ #define RCC_PLLCFG_PLLR_MASK (7 << RCC_PLLCFG_PLLR_SHIFT) #define RCC_PLLCFG_PLLR(n) ((n-1) << RCC_PLLCFG_PLLR_SHIFT) diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_syscfg.h b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_syscfg.h index 40a0963..befec72 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_syscfg.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_syscfg.h @@ -110,33 +110,33 @@ /* SYSCFG memory remap register */ -#define SYSCFG_CFGR1_MEMMODE_SHIFT (0) /* Bits 1:0 MEM_MODE: Memory mapping selection */ +#define SYSCFG_CFGR1_MEMMODE_SHIFT (0) /* Bits 1:0 MEM_MODE: Memory mapping selection */ #define SYSCFG_CFGR1_MEMMODE_MASK (3 << SYSCFG_CFGR1_MEMMODE_SHIFT) # define SYSCFG_CFGR1_MEMMODE_FLASH (0 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 00: Main Flash at 0x00000000 */ # define SYSCFG_CFGR1_MEMMODE_SYSTEM (1 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 01: System Flash at 0x00000000 */ # define SYSCFG_CFGR1_MEMMODE_SRAM (3 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 11: Embedded SRAM at 0x00000000 */ - /* Bit 2: Reserved */ -#define SYSCFG_CFGR1_PA11_RMP (1 << 3) /* Bit 3: PA11 remapping bit */ -#define SYSCFG_CFGR1_PA12_RMP (1 << 4) /* Bit 4: PA12 remapping bit */ -#define SYSCFG_CFGR1_IRPOL (1 << 5) /* Bit 5: IR output polarity selection */ -#define SYSCFG_CFGR1_IRMOD_SHIFT (6) /* Bits 6-7: IR Modulation Envelope signal selection */ + /* Bit 2: Reserved */ +#define SYSCFG_CFGR1_PA11_RMP (1 << 3) /* Bit 3: PA11 remapping bit */ +#define SYSCFG_CFGR1_PA12_RMP (1 << 4) /* Bit 4: PA12 remapping bit */ +#define SYSCFG_CFGR1_IRPOL (1 << 5) /* Bit 5: IR output polarity selection */ +#define SYSCFG_CFGR1_IRMOD_SHIFT (6) /* Bits 6-7: IR Modulation Envelope signal selection */ #define SYSCFG_CFGR1_IRMOD_MASK (3 << SYSCFG_CFGR1_IRMOD_SHIFT) -# define SYSCFG_CFGR1_IRMOD_TIM16 (0 << SYSCFG_CFGR1_IRMOD_SHIFT) /* 00: TIM16 selected */ -# define SYSCFG_CFGR1_IRMOD_USART1 (1 << SYSCFG_CFGR1_IRMOD_SHIFT) /* 01: USART1 selected */ -# define SYSCFG_CFGR1_IRMOD_USART4 (2 << SYSCFG_CFGR1_IRMOD_SHIFT) /* 10: USART1 selected */ -#define SYSCFG_CFGR1_BOOSTEN (1 << 8) /* Bit 8: IO analog switch voltage booster enable */ -#define SYSCFG_CFGR1_UCPD1STROBE (1 << 9) /* Bit 9: UCPD1 pull-down configuration strobe */ -#define SYSCFG_CFGR1_UCPD2STROBE (1 << 10) /* Bit 10: UCPD2 pull-down configuration strobe */ - /* Bits 11-15: Reserved */ -#define SYSCFG_CFGR1_I2CPB6FMP (1 << 16) /* Bit 16: */ -#define SYSCFG_CFGR1_I2CPB7FMP (1 << 17) /* Bit 17: */ -#define SYSCFG_CFGR1_I2CPB8FMP (1 << 18) /* Bit 18: */ -#define SYSCFG_CFGR1_I2CPB9FMP (1 << 19) /* Bit 19: */ -#define SYSCFG_CFGR1_I2C1FMP (1 << 20) /* Bit 20: */ -#define SYSCFG_CFGR1_I2C2FMP (1 << 21) /* Bit 21: */ -#define SYSCFG_CFGR1_I2CPA9FMP (1 << 22) /* Bit 22: */ -#define SYSCFG_CFGR1_I2CPA10FMP (1 << 23) /* Bit 23: */ - /* Bits 24-31: Reserved */ +# define SYSCFG_CFGR1_IRMOD_TIM16 (0 << SYSCFG_CFGR1_IRMOD_SHIFT) /* 00: TIM16 selected */ +# define SYSCFG_CFGR1_IRMOD_USART1 (1 << SYSCFG_CFGR1_IRMOD_SHIFT) /* 01: USART1 selected */ +# define SYSCFG_CFGR1_IRMOD_USART4 (2 << SYSCFG_CFGR1_IRMOD_SHIFT) /* 10: USART1 selected */ +#define SYSCFG_CFGR1_BOOSTEN (1 << 8) /* Bit 8: IO analog switch voltage booster enable */ +#define SYSCFG_CFGR1_UCPD1STROBE (1 << 9) /* Bit 9: UCPD1 pull-down configuration strobe */ +#define SYSCFG_CFGR1_UCPD2STROBE (1 << 10) /* Bit 10: UCPD2 pull-down configuration strobe */ + /* Bits 11-15: Reserved */ +#define SYSCFG_CFGR1_I2CPB6FMP (1 << 16) /* Bit 16: */ +#define SYSCFG_CFGR1_I2CPB7FMP (1 << 17) /* Bit 17: */ +#define SYSCFG_CFGR1_I2CPB8FMP (1 << 18) /* Bit 18: */ +#define SYSCFG_CFGR1_I2CPB9FMP (1 << 19) /* Bit 19: */ +#define SYSCFG_CFGR1_I2C1FMP (1 << 20) /* Bit 20: */ +#define SYSCFG_CFGR1_I2C2FMP (1 << 21) /* Bit 21: */ +#define SYSCFG_CFGR1_I2CPA9FMP (1 << 22) /* Bit 22: */ +#define SYSCFG_CFGR1_I2CPA10FMP (1 << 23) /* Bit 23: */ + /* Bits 24-31: Reserved */ /* SYSCFG interrupt line 0 status register */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_rcc.h b/arch/arm/src/stm32f0l0g0/hardware/stm32l0_rcc.h index aa31acc..1d84c0f 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_rcc.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32l0_rcc.h @@ -102,11 +102,11 @@ /* Internal clock sources calibration register */ -#define RCC_ICSCR_HSICAL_SHIFT (0) /* Bits 0-7: Internal high speed clock calibration */ +#define RCC_ICSCR_HSICAL_SHIFT (0) /* Bits 0-7: Internal high speed clock calibration */ #define RCC_ICSCR_HSICAL_MASK (0xff << RCC_ICSCR_HSICAL_SHIFT) -#define RCC_ICSCR_HSITRIM_SHIFT (8) /* Bits 8-12: High speed internal clock trimming */ +#define RCC_ICSCR_HSITRIM_SHIFT (8) /* Bits 8-12: High speed internal clock trimming */ #define RCC_ICSCR_HSITRIM_MASK (0x1f << RCC_ICSCR_HSITRIM_SHIFT) -#define RCC_ICSCR_MSIRANGE_SHIFT (13) /* Bits 13-15: MSI clock ranges */ +#define RCC_ICSCR_MSIRANGE_SHIFT (13) /* Bits 13-15: MSI clock ranges */ #define RCC_ICSCR_MSIRANGE_MASK (7 << RCC_ICSCR_MSIRANGE_SHIFT) # define RCC_ICSCR_MSIRANGE_0 (0 << RCC_ICSCR_MSIRANGE_SHIFT) /* 000: Range 0 around 65.536 kHz */ # define RCC_ICSCR_MSIRANGE_1 (1 << RCC_ICSCR_MSIRANGE_SHIFT) /* 001: Range 1 around 131.072 kHz */ @@ -115,9 +115,9 @@ # define RCC_ICSCR_MSIRANGE_4 (4 << RCC_ICSCR_MSIRANGE_SHIFT) /* 100: Range 4 around 1.048 MHz */ # define RCC_ICSCR_MSIRANGE_5 (5 << RCC_ICSCR_MSIRANGE_SHIFT) /* 101: Range 5 around 2.097 MHz (reset value) */ # define RCC_ICSCR_MSIRANGE_6 (6 << RCC_ICSCR_MSIRANGE_SHIFT) /* 110: Range 6 around 4.194 MHz */ -#define RCC_ICSCR_MSICAL_SHIFT (16) /* Bits 16-23: MSI clock calibration */ +#define RCC_ICSCR_MSICAL_SHIFT (16) /* Bits 16-23: MSI clock calibration */ #define RCC_ICSCR_MSICAL_MASK (0xff << RCC_ICSCR_MSICAL_SHIFT) -#define RCC_ICSCR_MSITRIM_SHIFT (24) /* Bits 24-31: MSI clock trimming */ +#define RCC_ICSCR_MSITRIM_SHIFT (24) /* Bits 24-31: MSI clock trimming */ #define RCC_ICSCR_MSITRIM_MASK (0xff << RCC_ICSCR_MSITRIM_SHIFT) #define RCC_ICSR_RSTVAL 0x0000b000 @@ -134,48 +134,48 @@ /* Clock configuration register */ -#define RCC_CFGR_SW_SHIFT (0) /* Bits 0-1: System clock Switch */ +#define RCC_CFGR_SW_SHIFT (0) /* Bits 0-1: System clock Switch */ #define RCC_CFGR_SW_MASK (3 << RCC_CFGR_SW_SHIFT) -# define RCC_CFGR_SW_MSI (0 << RCC_CFGR_SW_SHIFT) /* 00: MSI selected as system clock */ -# define RCC_CFGR_SW_HSI (1 << RCC_CFGR_SW_SHIFT) /* 01: HSI selected as system clock */ -# define RCC_CFGR_SW_HSE (2 << RCC_CFGR_SW_SHIFT) /* 10: HSE selected as system clock */ -# define RCC_CFGR_SW_PLL (3 << RCC_CFGR_SW_SHIFT) /* 11: PLL selected as system clock */ -#define RCC_CFGR_SWS_SHIFT (2) /* Bits 2-3: System Clock Switch Status */ +# define RCC_CFGR_SW_MSI (0 << RCC_CFGR_SW_SHIFT) /* 00: MSI selected as system clock */ +# define RCC_CFGR_SW_HSI (1 << RCC_CFGR_SW_SHIFT) /* 01: HSI selected as system clock */ +# define RCC_CFGR_SW_HSE (2 << RCC_CFGR_SW_SHIFT) /* 10: HSE selected as system clock */ +# define RCC_CFGR_SW_PLL (3 << RCC_CFGR_SW_SHIFT) /* 11: PLL selected as system clock */ +#define RCC_CFGR_SWS_SHIFT (2) /* Bits 2-3: System Clock Switch Status */ #define RCC_CFGR_SWS_MASK (3 << RCC_CFGR_SWS_SHIFT) -# define RCC_CFGR_SWS_MSI (0 << RCC_CFGR_SWS_SHIFT) /* 00: MSI oscillator used as system clock */ -# define RCC_CFGR_SWS_HSI (1 << RCC_CFGR_SWS_SHIFT) /* 01: HSI oscillator used as system clock */ -# define RCC_CFGR_SWS_HSE (2 << RCC_CFGR_SWS_SHIFT) /* 10: HSE oscillator used as system clock */ -# define RCC_CFGR_SWS_PLL (3 << RCC_CFGR_SWS_SHIFT) /* 11: PLL used as system clock */ -#define RCC_CFGR_HPRE_SHIFT (4) /* Bits 4-7: AHB prescaler */ +# define RCC_CFGR_SWS_MSI (0 << RCC_CFGR_SWS_SHIFT) /* 00: MSI oscillator used as system clock */ +# define RCC_CFGR_SWS_HSI (1 << RCC_CFGR_SWS_SHIFT) /* 01: HSI oscillator used as system clock */ +# define RCC_CFGR_SWS_HSE (2 << RCC_CFGR_SWS_SHIFT) /* 10: HSE oscillator used as system clock */ +# define RCC_CFGR_SWS_PLL (3 << RCC_CFGR_SWS_SHIFT) /* 11: PLL used as system clock */ +#define RCC_CFGR_HPRE_SHIFT (4) /* Bits 4-7: AHB prescaler */ #define RCC_CFGR_HPRE_MASK (0x0f << RCC_CFGR_HPRE_SHIFT) -# define RCC_CFGR_HPRE_SYSCLK (0 << RCC_CFGR_HPRE_SHIFT) /* 0xxx: SYSCLK not divided */ -# define RCC_CFGR_HPRE_SYSCLKd2 (8 << RCC_CFGR_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */ -# define RCC_CFGR_HPRE_SYSCLKd4 (9 << RCC_CFGR_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */ +# define RCC_CFGR_HPRE_SYSCLK (0 << RCC_CFGR_HPRE_SHIFT) /* 0xxx: SYSCLK not divided */ +# define RCC_CFGR_HPRE_SYSCLKd2 (8 << RCC_CFGR_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */ +# define RCC_CFGR_HPRE_SYSCLKd4 (9 << RCC_CFGR_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */ # define RCC_CFGR_HPRE_SYSCLKd8 (10 << RCC_CFGR_HPRE_SHIFT) /* 1010: SYSCLK divided by 8 */ # define RCC_CFGR_HPRE_SYSCLKd16 (11 << RCC_CFGR_HPRE_SHIFT) /* 1011: SYSCLK divided by 16 */ # define RCC_CFGR_HPRE_SYSCLKd64 (12 << RCC_CFGR_HPRE_SHIFT) /* 1100: SYSCLK divided by 64 */ # define RCC_CFGR_HPRE_SYSCLKd128 (13 << RCC_CFGR_HPRE_SHIFT) /* 1101: SYSCLK divided by 128 */ # define RCC_CFGR_HPRE_SYSCLKd256 (14 << RCC_CFGR_HPRE_SHIFT) /* 1110: SYSCLK divided by 256 */ # define RCC_CFGR_HPRE_SYSCLKd512 (15 << RCC_CFGR_HPRE_SHIFT) /* 1111: SYSCLK divided by 512 */ -#define RCC_CFGR_PPRE1_SHIFT (8) /* Bits 8-10: APB Low speed prescaler (APB1) */ +#define RCC_CFGR_PPRE1_SHIFT (8) /* Bits 8-10: APB Low speed prescaler (APB1) */ #define RCC_CFGR_PPRE1_MASK (7 << RCC_CFGR_PPRE1_SHIFT) # define RCC_CFGR_PPRE1_HCLK (0 << RCC_CFGR_PPRE1_SHIFT) /* 0xx: HCLK not divided */ # define RCC_CFGR_PPRE1_HCLKd2 (4 << RCC_CFGR_PPRE1_SHIFT) /* 100: HCLK divided by 2 */ # define RCC_CFGR_PPRE1_HCLKd4 (5 << RCC_CFGR_PPRE1_SHIFT) /* 101: HCLK divided by 4 */ # define RCC_CFGR_PPRE1_HCLKd8 (6 << RCC_CFGR_PPRE1_SHIFT) /* 110: HCLK divided by 8 */ # define RCC_CFGR_PPRE1_HCLKd16 (7 << RCC_CFGR_PPRE1_SHIFT) /* 111: HCLK divided by 16 */ -#define RCC_CFGR_PPRE2_SHIFT (11) /* Bits 11-13: APB High speed prescaler (APB2) */ +#define RCC_CFGR_PPRE2_SHIFT (11) /* Bits 11-13: APB High speed prescaler (APB2) */ #define RCC_CFGR_PPRE2_MASK (7 << RCC_CFGR_PPRE2_SHIFT) # define RCC_CFGR_PPRE2_HCLK (0 << RCC_CFGR_PPRE2_SHIFT) /* 0xx: HCLK not divided */ # define RCC_CFGR_PPRE2_HCLKd2 (4 << RCC_CFGR_PPRE2_SHIFT) /* 100: HCLK divided by 2 */ # define RCC_CFGR_PPRE2_HCLKd4 (5 << RCC_CFGR_PPRE2_SHIFT) /* 101: HCLK divided by 4 */ # define RCC_CFGR_PPRE2_HCLKd8 (6 << RCC_CFGR_PPRE2_SHIFT) /* 110: HCLK divided by 8 */ # define RCC_CFGR_PPRE2_HCLKd16 (7 << RCC_CFGR_PPRE2_SHIFT) /* 111: HCLK divided by 16 */ - /* Bits 14: Reserved */ -#define RCC_CFGR_STOPWUCK (15) /* Bits 15: */ -#define RCC_CFGR_PLLSRC (1 << 16) /* Bit 16: PLL entry clock source */ - /* Bit 17: Reserved */ -#define RCC_CFGR_PLLMUL_SHIFT (18) /* Bits 18-21: PLL Multiplication Factor */ + /* Bits 14: Reserved */ +#define RCC_CFGR_STOPWUCK (15) /* Bits 15: */ +#define RCC_CFGR_PLLSRC (1 << 16) /* Bit 16: PLL entry clock source */ + /* Bit 17: Reserved */ +#define RCC_CFGR_PLLMUL_SHIFT (18) /* Bits 18-21: PLL Multiplication Factor */ #define RCC_CFGR_PLLMUL_MASK (15 << RCC_CFGR_PLLMUL_SHIFT) # define RCC_CFGR_PLLMUL_CLKx3 (0 << RCC_CFGR_PLLMUL_SHIFT) /* 0000: PLL clock entry x 3 */ # define RCC_CFGR_PLLMUL_CLKx4 (1 << RCC_CFGR_PLLMUL_SHIFT) /* 0001: PLL clock entry x 4 */ @@ -186,12 +186,12 @@ # define RCC_CFGR_PLLMUL_CLKx24 (6 << RCC_CFGR_PLLMUL_SHIFT) /* 0110: PLL clock entry x 24 */ # define RCC_CFGR_PLLMUL_CLKx32 (7 << RCC_CFGR_PLLMUL_SHIFT) /* 0111: PLL clock entry x 32 */ # define RCC_CFGR_PLLMUL_CLKx48 (8 << RCC_CFGR_PLLMUL_SHIFT) /* 1000: PLL clock entry x 48 */ -#define RCC_CFGR_PLLDIV_SHIFT (22) /* Bits 22-23: PLL output division */ +#define RCC_CFGR_PLLDIV_SHIFT (22) /* Bits 22-23: PLL output division */ #define RCC_CFGR_PLLDIV_MASK (3 << RCC_CFGR_PLLDIV_SHIFT) # define RCC_CFGR_PLLDIV_2 (1 << RCC_CFGR_PLLDIV_SHIFT) /* 01: PLL clock output = PLLVCO / 2 */ # define RCC_CFGR_PLLDIV_3 (2 << RCC_CFGR_PLLDIV_SHIFT) /* 10: PLL clock output = PLLVCO / 3 */ # define RCC_CFGR_PLLDIV_4 (3 << RCC_CFGR_PLLDIV_SHIFT) /* 11: PLL clock output = PLLVCO / 4 */ -#define RCC_CFGR_MCOSEL_SHIFT (24) /* Bits 24-27: Microcontroller clock output selection */ +#define RCC_CFGR_MCOSEL_SHIFT (24) /* Bits 24-27: Microcontroller clock output selection */ #define RCC_CFGR_MCOSEL_MASK (7 << RCC_CFGR_MCOSEL_SHIFT) # define RCC_CFGR_MCOSEL_DISABLED (0 << RCC_CFGR_MCOSEL_SHIFT) /* 0000: MCO output disabled, no clock on MCO */ # define RCC_CFGR_MCOSEL_SYSCLK (1 << RCC_CFGR_MCOSEL_SHIFT) /* 0001: SYSCLK clock selected */ @@ -202,14 +202,14 @@ # define RCC_CFGR_MCOSEL_LSICLK (6 << RCC_CFGR_MCOSEL_SHIFT) /* 0110: LSI oscillator clock selected */ # define RCC_CFGR_MCOSEL_LSECLK (7 << RCC_CFGR_MCOSEL_SHIFT) /* 0111: LSE oscillator clock selected */ # define RCC_CFGR_MCOSEL_HSI48CLK (8 << RCC_CFGR_MCOSEL_SHIFT) /* 1000: HSI48 oscillator clock selected */ -#define RCC_CFGR_MCOPRE_SHIFT (28) /* Bits 28-30: Microcontroller clock output selection */ +#define RCC_CFGR_MCOPRE_SHIFT (28) /* Bits 28-30: Microcontroller clock output selection */ #define RCC_CFGR_MCOPRE_MASK (7 << RCC_CFGR_MCOPRE_SHIFT) # define RCC_CFGR_MCOPRE_DIV1 (0 << RCC_CFGR_MCOPRE_SHIFT) /* 000: MCO is divided by 1 */ # define RCC_CFGR_MCOPRE_DIV2 (1 << RCC_CFGR_MCOPRE_SHIFT) /* 001: MCO is divided by 2 */ # define RCC_CFGR_MCOPRE_DIV4 (2 << RCC_CFGR_MCOPRE_SHIFT) /* 010: MCO is divided by 4 */ # define RCC_CFGR_MCOPRE_DIV8 (3 << RCC_CFGR_MCOPRE_SHIFT) /* 011: MCO is divided by 8 */ # define RCC_CFGR_MCOPRE_DIV16 (4 << RCC_CFGR_MCOPRE_SHIFT) /* 100: MCO is divided by 16 */ - /* Bit 31: Reserved */ + /* Bit 31: Reserved */ #define RCC_CFGR_RESET 0x00000000 /* Clock Source Interrupt enable register */ @@ -338,7 +338,7 @@ #define RCC_AHBENR_RNGEN (1 << 20) /* Bit 20: Random number generator module clock enable */ /* Bits 21-23: Reserved */ #define RCC_AHBENR_AESEN (1 << 24) /* Bit 24: Crypto module (AES) clock enable */ - /* Bits 25-31: Reserved */ + /* Bits 25-31: Reserved */ /* APB2 Peripheral Clock enable register */ @@ -516,8 +516,8 @@ # define RCC_CSR_LSEDRV_HIGH (3 << RCC_CSR_LSEDRV_SHIFT) #define RCC_CSR_CSSLSEON (1 << 13) /* Bit 13: CSS on LSE enable */ #define RCC_CSR_CSSLSED (1 << 14) /* Bit 14: CSS on LSE failure detection flag */ - /* Bit 15: Reserved */ -#define RCC_CSR_RTCSEL_SHIFT (16) /* Bits 16-17: RTC clock source selection */ + /* Bit 15: Reserved */ +#define RCC_CSR_RTCSEL_SHIFT (16) /* Bits 16-17: RTC clock source selection */ #define RCC_CSR_RTCSEL_MASK (3 << RCC_CSR_RTCSEL_SHIFT) # define RCC_CSR_RTCSEL_NOCLK (0 << RCC_CSR_RTCSEL_SHIFT) # define RCC_CSR_RTCSEL_LSE (1 << RCC_CSR_RTCSEL_SHIFT) diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_syscfg.h b/arch/arm/src/stm32f0l0g0/hardware/stm32l0_syscfg.h index a6b040d..0cbbcea 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_syscfg.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32l0_syscfg.h @@ -34,17 +34,17 @@ /* Register Offsets *********************************************************************************/ -#define STM32_SYSCFG_CFGR1_OFFSET 0x0000 /* SYSCFG configuration register 1 */ -#define STM32_SYSCFG_CFGR2_OFFSET 0x0004 /* SYSCFG configuration register 2 */ -#define STM32_SYSCFG_CFGR3_OFFSET 0x0020 /* SYSCFG configuration register 3 */ +#define STM32_SYSCFG_CFGR1_OFFSET 0x0000 /* SYSCFG configuration register 1 */ +#define STM32_SYSCFG_CFGR2_OFFSET 0x0004 /* SYSCFG configuration register 2 */ +#define STM32_SYSCFG_CFGR3_OFFSET 0x0020 /* SYSCFG configuration register 3 */ #define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ -#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ -#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ -#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ -#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ +#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ +#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ +#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ +#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ -#define STM32_SYSCFG_CFGR3_OFFSET 0x0020 /* SYSCFG configuration register 3 */ +#define STM32_SYSCFG_CFGR3_OFFSET 0x0020 /* SYSCFG configuration register 3 */ /* Register Addresses *******************************************************************************/ diff --git a/arch/arm/src/stm32f0l0g0/stm32_adc.h b/arch/arm/src/stm32f0l0g0/stm32_adc.h index 3e02ede..d9b1bc7 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_adc.h +++ b/arch/arm/src/stm32f0l0g0/stm32_adc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32/stm32_adc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_ADC_H #define __ARCH_ARM_SRC_STM32F0L0G0_STM32_ADC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include <nuttx/config.h> @@ -34,10 +34,11 @@ #include "hardware/stm32_adc.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* Configuration ********************************************************************/ + ****************************************************************************/ + +/* Configuration ************************************************************/ /* Timer ADC trigger not supported yet */ @@ -72,9 +73,10 @@ # define ADC1_EXTSEL_T2TRGO ADC12_CFGR1_EXTSEL_TRG2 # define ADC1_EXTSEL_T3TRGO ADC12_CFGR1_EXTSEL_TRG3 # define ADC1_EXTSEL_T15TRGO ADC12_CFGR1_EXTSEL_TRG4 - /* TRG5 reserved */ - /* TRG6 reserved */ - /* TRG7 reserved */ + /* TRG5 reserved + * TRG6 reserved + * TRG7 reserved + */ #elif defined(CONFIG_STM32F0L0G0_STM32L0) /* TRG0 reserved */ # define ADC1_EXTSEL_T21CC2 ADC12_CFGR1_EXTSEL_TRG1 @@ -98,6 +100,7 @@ #endif /* EXTSEL configuration *****************************************************/ + /* TODO */ /* ADC interrupts ***********************************************************/ @@ -112,7 +115,7 @@ #define ADC_ISR_ALLINTS (ADC_ISR_EOC | ADC_ISR_AWD | ADC_ISR_OVR) #define ADC_IER_ALLINTS (ADC_IER_EOC | ADC_IER_AWD | ADC_IER_OVR) -/* ADC registers ***********************************************************/ +/* ADC registers ************************************************************/ #define STM32_ADC_DMAREG_OFFSET STM32_ADC_CFGR1_OFFSET #define ADC_DMAREG_DMA ADC_CFGR1_DMAEN @@ -144,14 +147,15 @@ #define ADC_DUMP_REGS(adc) \ (adc)->llops->dump_regs(adc) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/* On STM32F42xx and STM32F43xx devices,VBAT and temperature sensor are connected - * to the same ADC internal channel (ADC1_IN18). Only one conversion, either - * temperature sensor or VBAT, must be selected at a time. When both conversion are - * enabled simultaneously, only the VBAT conversion is performed. +/* On STM32F42xx and STM32F43xx devices,VBAT and temperature sensor are + * connected to the same ADC internal channel (ADC1_IN18). Only one + * conversion, either temperature sensor or VBAT, must be selected at a time. + * When both conversion are enabled simultaneously, only the VBAT conversion + * is performed. */ enum adc_io_cmds_e @@ -198,7 +202,9 @@ typedef struct adc_channel_s { uint8_t channel:5; - /* Sampling time individually for each channel. It differs between families */ + /* Sampling time individually for each channel. + * It differs between families + */ uint8_t sample_time:3; } adc_channel_t; @@ -256,7 +262,8 @@ struct stm32_adc_ops_s /* Register buffer for ADC DMA transfer */ - int (*regbuf_reg)(FAR struct stm32_adc_dev_s *dev, uint16_t *buffer, uint8_t len); + int (*regbuf_reg)(FAR struct stm32_adc_dev_s *dev, uint16_t *buffer, + uint8_t len); /* Start/stop regular conversion */ @@ -278,9 +285,9 @@ struct stm32_adc_ops_s #endif /* CONFIG_STM32F0L0G0_ADC_LL_OPS */ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ #ifdef __cplusplus @@ -311,12 +318,13 @@ struct adc_dev_s; struct adc_dev_s *stm32_adcinitialize(int intf, FAR const uint8_t *chanlist, int channels); -/************************************************************************************ +/**************************************************************************** * Name: stm32_adc_llops_get - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS -FAR const struct stm32_adc_ops_s *stm32_adc_llops_get(FAR struct adc_dev_s *dev); +FAR const struct stm32_adc_ops_s +*stm32_adc_llops_get(FAR struct adc_dev_s *dev); #endif #undef EXTERN diff --git a/arch/arm/src/stm32f0l0g0/stm32_lowputc.c b/arch/arm/src/stm32f0l0g0/stm32_lowputc.c index 833c8f1..501c179 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_lowputc.c +++ b/arch/arm/src/stm32f0l0g0/stm32_lowputc.c @@ -25,10 +25,6 @@ #include <nuttx/config.h> #include "chip.h" -/**************************************************************************** - * Public Functions - ****************************************************************************/ - #if defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V1) # include "stm32_lowputc_v1.c" #elif defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V2) @@ -36,3 +32,7 @@ #else # error "Unsupported STM32 M0 serial" #endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/arch/arm/src/stm32f0l0g0/stm32l0_rcc.c b/arch/arm/src/stm32f0l0g0/stm32l0_rcc.c index 7aa4cb3..a39a96e 100644 --- a/arch/arm/src/stm32f0l0g0/stm32l0_rcc.c +++ b/arch/arm/src/stm32f0l0g0/stm32l0_rcc.c @@ -486,7 +486,8 @@ static void stm32_stdclockconfig(void) putreg32(regval, STM32_RCC_APB1ENR); /* Go to the high performance voltage range 1 if necessary. In this mode, - * the PLL VCO frequency can be up to 96MHz. USB and SDIO can be supported. + * the PLL VCO frequency can be up to 96MHz. + * USB and SDIO can be supported. * * Range 1: PLLVCO up to 96MHz in range 1 (1.8V) * Range 2: PLLVCO up to 48MHz in range 2 (1.5V) (default) @@ -601,25 +602,26 @@ static void stm32_stdclockconfig(void) #if (STM32_SYSCLK_SW != RCC_CFGR_SW_MSI) /* Increasing the CPU frequency (in the same voltage range): * - * After reset, the used clock is the MSI (2 MHz) with 0 WS configured in the - * FLASH_ACR register. 32-bit access is enabled and prefetch is disabled. - * ST strongly recommends to use the following software sequences to tune the - * number of wait states needed to access the Flash memory with the CPU - * frequency. + * After reset, the used clock is the MSI (2 MHz) with 0 WS configured in + * the FLASH_ACR register. 32-bit access is enabled and prefetch is + * disabled. ST strongly recommends to use the following software sequences + * to tune the number of wait states needed to access the Flash memory with + * the CPU frequency. * * - Program the 64-bit access by setting the ACC64 bit in Flash access * control register (FLASH_ACR) * - Check that 64-bit access is taken into account by reading FLASH_ACR * - Program 1 WS to the LATENCY bit in FLASH_ACR - * - Check that the new number of WS is taken into account by reading FLASH_ACR + * - Check that the new number of WS is taken into account by reading + * FLASH_ACR * - Modify the CPU clock source by writing to the SW bits in the Clock * configuration register (RCC_CFGR) - * - If needed, modify the CPU clock prescaler by writing to the HPRE bits in - * RCC_CFGR - * - Check that the new CPU clock source or/and the new CPU clock prescaler - * value is/are taken into account by reading the clock source status (SWS - * bits) or/and the AHB prescaler value (HPRE bits), respectively, in the - * RCC_CFGR register + * - If needed, modify the CPU clock prescaler by writing to the HPRE + * bits in RCC_CFGR + * - Check that the new CPU clock source or/and the new CPU clock + * prescaler value is/are taken into account by reading the clock + * source status (SWS bits) or/and the AHB prescaler value (HPRE bits), + * respectively, in the RCC_CFGR register */ regval = getreg32(STM32_FLASH_ACR); @@ -670,8 +672,8 @@ static void stm32_stdclockconfig(void) #if STM32_SYSCLK_SW == RCC_CFGR_SW_PLL /* Set the PLL divider and multiplier. NOTE: The PLL needs to be disabled - * to do these operation. We know this is the case here because pll_reset() - * was previously called by stm32_clockconfig(). + * to do these operation. We know this is the case here because + * pll_reset() was previously called by stm32_clockconfig(). */ regval = getreg32(STM32_RCC_CFGR); @@ -730,7 +732,6 @@ static void stm32_stdclockconfig(void) stm32_rcc_enablelse(); #endif - } #endif diff --git a/boards/arm/nrf52/nrf52840-dongle/src/nrf52840-dongle.h b/boards/arm/nrf52/nrf52840-dongle/src/nrf52840-dongle.h index 614a458..f332031 100644 --- a/boards/arm/nrf52/nrf52840-dongle/src/nrf52840-dongle.h +++ b/boards/arm/nrf52/nrf52840-dongle/src/nrf52840-dongle.h @@ -63,7 +63,7 @@ #ifndef __ASSEMBLY__ /**************************************************************************** - * Public Functions + * Public Functions Prototypes ****************************************************************************/ /**************************************************************************** diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/include/board.h b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/include/board.h index cd23a2c..4e4c802 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/include/board.h +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/include/board.h @@ -52,7 +52,9 @@ #define STM32_HSE_FREQUENCY STM32_BOARD_XTAL #define STM32_LSE_FREQUENCY 32768 /* X2 on board */ -/* PLL source is HSI/1, PLL multipler is 4: PLL frequency is 16MHz (XTAL) x 4 = 64MHz */ +/* PLL source is HSI/1, PLL multipler is 4: + * PLL frequency is 16MHz (XTAL) x 4 = 64MHz + */ #define STM32_CFGR_PLLSRC 0 #define STM32_CFGR_PLLXTPRE 0 diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/b-l072z-lrwan1.h b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/b-l072z-lrwan1.h index dd44a51..a58dd6a 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/b-l072z-lrwan1.h +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/b-l072z-lrwan1.h @@ -133,7 +133,8 @@ int stm32_bringup(void); * Name: stm32_spidev_initialize * * Description: - * Called to configure SPI chip select GPIO pins for the Nucleo-H743ZI board. + * Called to configure SPI chip select GPIO pins for the B-L072Z-LRWAN1 + * board. * ****************************************************************************/ @@ -141,11 +142,12 @@ int stm32_bringup(void); void stm32_spidev_initialize(void); #endif -/***************************************************************************** +/**************************************************************************** * Name: stm32_lpwaninitialize * * Description: * Initialize SX127X LPWAN interaface. + * ****************************************************************************/ #ifdef CONFIG_LPWAN_SX127X diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_boot.c b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_boot.c index f54f2e6..18e7945 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_boot.c +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_boot.c @@ -62,7 +62,6 @@ void stm32_boardinitialize(void) { - #ifdef CONFIG_ARCH_LEDS /* Configure on-board LEDs if LED support has been selected. */ @@ -80,22 +79,21 @@ void stm32_boardinitialize(void) * Name: board_late_initialize * * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional initialization call - * will be performed in the boot-up sequence to a function called - * board_late_initialize(). board_late_initialize() will be called immediately after - * up_initialize() is called and just before the initial application is started. - * This additional initialization phase may be used, for example, to initialize - * board-specific device drivers. + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. * ****************************************************************************/ #ifdef CONFIG_BOARD_LATE_INITIALIZE void board_late_initialize(void) { -#if defined(CONFIG_NSH_LIBRARY) && !defined(CONFIG_LIB_BOARDCTL) - /* Perform board bring-up here instead of from the board_app_initialize(). */ + /* Perform board-specific initialization */ - stm32_bringup(); -#endif + nrf52_bringup(); } #endif diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_bringup.c b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_bringup.c index 1bbf592..cc5c828 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_bringup.c +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_bringup.c @@ -120,7 +120,7 @@ static void stm32_i2ctool(void) * CONFIG_BOARD_LATE_INITIALIZE=y : * Called from board_late_initialize(). * - * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y && CONFIG_NSH_ARCHINIT: + * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y : * Called from the NSH library * ****************************************************************************/ @@ -164,7 +164,8 @@ int stm32_bringup(void) ret = stm32_lpwaninitialize(); if (ret < 0) { - syslog(LOG_ERR, "ERROR: Failed to initialize wireless driver: %d\n", ret); + syslog(LOG_ERR, "ERROR: Failed to initialize wireless driver: %d\n", + ret); } #endif /* CONFIG_LPWAN_SX127X */ diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_spi.c b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_spi.c index 984eb0d..f94c32f 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_spi.c +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_spi.c @@ -97,8 +97,8 @@ void stm32_spidev_initialize(void) * must be provided by board-specific logic. They are implementations of * the select and status methods of the SPI interface defined by struct * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. To use this - * common SPI logic on your board: + * stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: * * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select * pins. @@ -106,10 +106,10 @@ void stm32_spidev_initialize(void) * in your board-specific logic. These functions will perform chip * selection and status operations using GPIOs in the way your board is * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level application - * initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to bind - * the SPI driver to higher level logic (e.g., calling + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * @@ -119,14 +119,16 @@ void stm32_spidev_initialize(void) void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); switch (devid) { #ifdef CONFIG_LPWAN_SX127X case SPIDEV_LPWAN(0): { - spiinfo("SX127X device %s\n", selected ? "asserted" : "de-asserted"); + piinfo("SX127X device %s\n", + selected ? "asserted" : "de-asserted"); /* Set the GPIO low to select and high to de-select */ @@ -134,6 +136,7 @@ void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, break; } #endif + default: { break; @@ -154,6 +157,7 @@ uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) break; } #endif + default: { break; @@ -168,7 +172,8 @@ uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) void stm32_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/nucleo-g071rb.h b/boards/arm/stm32f0l0g0/nucleo-g071rb/src/nucleo-g071rb.h index 585dd84..0809a15 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/nucleo-g071rb.h +++ b/boards/arm/stm32f0l0g0/nucleo-g071rb/src/nucleo-g071rb.h @@ -82,7 +82,7 @@ * Public Function Prototypes ****************************************************************************/ -/***************************************************************************** +/**************************************************************************** * Name: stm32_bringup * * Description: diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_boot.c b/boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_boot.c index 69ed9ec..556b44a 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_boot.c +++ b/boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_boot.c @@ -63,22 +63,21 @@ void stm32_boardinitialize(void) * Name: board_late_initialize * * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional initialization call - * will be performed in the boot-up sequence to a function called - * board_late_initialize(). board_late_initialize() will be called immediately after - * up_initialize() is called and just before the initial application is started. - * This additional initialization phase may be used, for example, to initialize - * board-specific device drivers. + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. * ****************************************************************************/ #ifdef CONFIG_BOARD_LATE_INITIALIZE void board_late_initialize(void) { -#if defined(CONFIG_NSH_LIBRARY) && !defined(CONFIG_LIB_BOARDCTL) - /* Perform board bring-up here instead of from the board_app_initialize(). */ + /* Perform board-specific initialization */ stm32_bringup(); -#endif } #endif diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/include/board.h b/boards/arm/stm32f0l0g0/nucleo-l073rz/include/board.h index a1ac8b8..672a742 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/include/board.h +++ b/boards/arm/stm32f0l0g0/nucleo-l073rz/include/board.h @@ -53,7 +53,9 @@ #define STM32_HSE_FREQUENCY STM32_BOARD_XTAL #define STM32_LSE_FREQUENCY 32768 /* X2 on board */ -/* PLL source is HSE/1, PLL multipler is 8: PLL frequency is 8MHz (XTAL) x 8 = 64MHz */ +/* PLL source is HSE/1, PLL multipler is 8: + * PLL frequency is 8MHz (XTAL) x 8 = 64MHz + */ #define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC #define STM32_CFGR_PLLXTPRE 0 diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/nucleo-l073rz.h b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/nucleo-l073rz.h index c1e6c1f..36e5e2c 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/nucleo-l073rz.h +++ b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/nucleo-l073rz.h @@ -116,7 +116,7 @@ * Public Function Prototypes ****************************************************************************/ -/***************************************************************************** +/**************************************************************************** * Name: stm32_bringup * * Description: @@ -132,11 +132,12 @@ int stm32_bringup(void); -/***************************************************************************** +/**************************************************************************** * Name: stm32_spidev_initialize * * Description: - * Called to configure SPI chip select GPIO pins for the Nucleo-H743ZI board. + * Called to configure SPI chip select GPIO pins for the Nucleo-L073RZ + * board. * ****************************************************************************/ @@ -144,29 +145,31 @@ int stm32_bringup(void); void stm32_spidev_initialize(void); #endif -/***************************************************************************** +/**************************************************************************** * Name: stm32_wlinitialize * * Description: * Initialize NRF24L01 wireless interaface. + * ****************************************************************************/ #ifdef CONFIG_WL_NRF24L01 int stm32_wlinitialize(void); #endif -/***************************************************************************** +/**************************************************************************** * Name: stm32_lpwaninitialize * * Description: * Initialize SX127X LPWAN interaface. + * ****************************************************************************/ #ifdef CONFIG_LPWAN_SX127X int stm32_lpwaninitialize(void); #endif -/***************************************************************************** +/**************************************************************************** * Name: stm32_mfrc522initialize * * Description: diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_boot.c b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_boot.c index 0e607cc..619103d 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_boot.c +++ b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_boot.c @@ -79,22 +79,21 @@ void stm32_boardinitialize(void) * Name: board_late_initialize * * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional initialization call - * will be performed in the boot-up sequence to a function called - * board_late_initialize(). board_late_initialize() will be called immediately after - * up_initialize() is called and just before the initial application is started. - * This additional initialization phase may be used, for example, to initialize - * board-specific device drivers. + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. * ****************************************************************************/ #ifdef CONFIG_BOARD_LATE_INITIALIZE void board_late_initialize(void) { -#if defined(CONFIG_NSH_LIBRARY) && !defined(CONFIG_LIB_BOARDCTL) - /* Perform board bring-up here instead of from the board_app_initialize(). */ + /* Perform board-specific initialization */ stm32_bringup(); -#endif } #endif diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_bringup.c b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_bringup.c index 5c8990f..21fdc77 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_bringup.c +++ b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_bringup.c @@ -61,7 +61,7 @@ * CONFIG_BOARD_LATE_INITIALIZE=y : * Called from board_late_initialize(). * - * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y && CONFIG_NSH_ARCHINIT: + * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y : * Called from the NSH library * ****************************************************************************/ @@ -125,7 +125,8 @@ int stm32_bringup(void) ret = stm32_wlinitialize(); if (ret < 0) { - syslog(LOG_ERR, "ERROR: Failed to initialize wireless driver: %d\n", ret); + syslog(LOG_ERR, "ERROR: Failed to initialize wireless driver: %d\n", + ret); } #endif /* CONFIG_WL_NRF24L01 */ @@ -133,7 +134,8 @@ int stm32_bringup(void) ret = stm32_lpwaninitialize(); if (ret < 0) { - syslog(LOG_ERR, "ERROR: Failed to initialize wireless driver: %d\n", ret); + syslog(LOG_ERR, "ERROR: Failed to initialize wireless driver: %d\n", + ret); } #endif /* CONFIG_LPWAN_SX127X */ diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_spi.c b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_spi.c index ac71a55..7ca6f90 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_spi.c +++ b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_spi.c @@ -117,8 +117,8 @@ void stm32_spidev_initialize(void) * must be provided by board-specific logic. They are implementations of * the select and status methods of the SPI interface defined by struct * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. To use this - * common SPI logic on your board: + * stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: * * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select * pins. @@ -126,19 +126,21 @@ void stm32_spidev_initialize(void) * in your board-specific logic. These functions will perform chip * selection and status operations using GPIOs in the way your board is * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level application - * initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to bind - * the SPI driver to higher level logic (e.g., calling + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * ****************************************************************************/ #ifdef CONFIG_STM32F0L0G0_SPI1 -void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, + bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); switch (devid) { @@ -154,10 +156,12 @@ void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) break; } #endif + #ifdef CONFIG_LPWAN_SX127X case SPIDEV_LPWAN(0): { - spiinfo("SX127X device %s\n", selected ? "asserted" : "de-asserted"); + spiinfo("SX127X device %s\n", + selected ? "asserted" : "de-asserted"); /* Set the GPIO low to select and high to de-select */ @@ -165,6 +169,7 @@ void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) break; } #endif + default: { break; @@ -185,6 +190,7 @@ uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) break; } #endif + #ifdef CONFIG_LPWAN_SX127X case SPIDEV_LPWAN(0): { @@ -192,6 +198,7 @@ uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) break; } #endif + default: { break; @@ -206,7 +213,8 @@ uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) void stm32_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); switch (devid) { @@ -216,6 +224,7 @@ void stm32_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, stm32_gpiowrite(GPIO_MFRC522_CS, !selected); } #endif + default: { break; @@ -236,6 +245,7 @@ uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) break; } #endif + default: { break; diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_sx127x.c b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_sx127x.c index abc7188..2385567 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_sx127x.c +++ b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_sx127x.c @@ -165,7 +165,8 @@ static int sx127x_pa_select(bool enable) if (enable == false) { ret = -EINVAL; - wlerr("Module supports only PA_BOOST pin, so PA_SELECT must be enabled!\n"); + wlerr("Module supports only PA_BOOST pin, " + "so PA_SELECT must be enabled!\n"); } return ret; diff --git a/drivers/power/motor.c b/drivers/power/motor.c index 944b5b1..99e431b 100644 --- a/drivers/power/motor.c +++ b/drivers/power/motor.c @@ -48,7 +48,8 @@ static ssize_t motor_read(FAR struct file *filep, FAR char *buffer, size_t buflen); static ssize_t motor_write(FAR struct file *filep, FAR const char *buffer, size_t buflen); -static int motor_ioctl(FAR struct file *filep, int cmd, unsigned long arg); +static int motor_ioctl(FAR struct file *filep, int cmd, + unsigned long arg); /**************************************************************************** * Private Data @@ -93,8 +94,8 @@ static int motor_open(FAR struct file *filep) if (ret >= 0) { /* Increment the count of references to the device. If this the first - * time that the driver has been opened for this device, then initialize - * the device. + * time that the driver has been opened for this device, then + * initialize the device. */ tmp = dev->ocount + 1; @@ -106,7 +107,9 @@ static int motor_open(FAR struct file *filep) } else { - /* Check if this is the first time that the driver has been opened. */ + /* Check if this is the first time that the driver has been + * opened. + */ if (tmp == 1) { @@ -166,7 +169,7 @@ static int motor_close(FAR struct file *filep) /* Free the IRQ and disable the motor device */ - flags = enter_critical_section(); /* Disable interrupts */ + flags = enter_critical_section(); /* Disable interrupts */ dev->ops->shutdown(dev); /* Disable the motor */ leave_critical_section(flags); @@ -181,7 +184,8 @@ static int motor_close(FAR struct file *filep) * Name: motor_read ****************************************************************************/ -static ssize_t motor_read(FAR struct file *filep, FAR char *buffer, size_t buflen) +static ssize_t motor_read(FAR struct file *filep, FAR char *buffer, + size_t buflen) { return 1; } @@ -429,7 +433,8 @@ static int motor_ioctl(FAR struct file *filep, int cmd, unsigned long arg) if (params->position < 0.0 || params->position > motor->limits.position) { - pwrerr("ERROR: params->position > limits.position: %.2f > %.2f\n", + pwrerr("ERROR: params->position > limits.position: " + "%.2f > %.2f\n", params->position, motor->limits.position); ret = -EPERM; @@ -440,7 +445,8 @@ static int motor_ioctl(FAR struct file *filep, int cmd, unsigned long arg) #ifdef CONFIG_MOTOR_HAVE_SPEED /* Check speed configuration */ - if (motor->limits.speed > 0.0 && params->speed > motor->limits.speed) + if (motor->limits.speed > 0.0 && + params->speed > motor->limits.speed) { pwrerr("ERROR: params->speed > limits.speed: %.2f > %.2f\n", params->speed, motor->limits.speed); @@ -453,7 +459,8 @@ static int motor_ioctl(FAR struct file *filep, int cmd, unsigned long arg) #ifdef CONFIG_MOTOR_HAVE_TORQUE /* Check torque configuration */ - if (motor->limits.torque > 0.0 && params->torque > motor->limits.torque) + if (motor->limits.torque > 0.0 && + params->torque > motor->limits.torque) { pwrerr("ERROR: params->torque > limits.torque: %.2f > %.2f\n", params->torque, motor->limits.torque); @@ -466,7 +473,8 @@ static int motor_ioctl(FAR struct file *filep, int cmd, unsigned long arg) #ifdef CONFIG_MOTOR_HAVE_FORCE /* Check force configuration */ - if (motor->limits.force > 0.0 && params->force > motor->limits.force) + if (motor->limits.force > 0.0 && + params->force > motor->limits.force) { pwrerr("ERROR: params->force > limits.force: %.2f > %.2f\n", params->force, motor->limits.force); @@ -504,7 +512,8 @@ errout: * Name: motor_register ****************************************************************************/ -int motor_register(FAR const char *path, FAR struct motor_dev_s *dev, FAR void *lower) +int motor_register(FAR const char *path, FAR struct motor_dev_s *dev, + FAR void *lower) { int ret; diff --git a/drivers/power/powerled.c b/drivers/power/powerled.c index 7800da7..13fa721 100644 --- a/drivers/power/powerled.c +++ b/drivers/power/powerled.c @@ -44,7 +44,8 @@ static int powerled_open(FAR struct file *filep); static int powerled_close(FAR struct file *filep); -static int powerled_ioctl(FAR struct file *filep, int cmd, unsigned long arg); +static int powerled_ioctl(FAR struct file *filep, int cmd, + unsigned long arg); /**************************************************************************** * Private Data @@ -89,8 +90,8 @@ static int powerled_open(FAR struct file *filep) if (ret >= 0) { /* Increment the count of references to the device. If this the first - * time that the driver has been opened for this device, then initialize - * the device. + * time that the driver has been opened for this device, then + * initialize the device. */ tmp = dev->ocount + 1; @@ -102,7 +103,9 @@ static int powerled_open(FAR struct file *filep) } else { - /* Check if this is the first time that the driver has been opened. */ + /* Check if this is the first time that the driver has been + * opened. + */ if (tmp == 1) { @@ -163,7 +166,7 @@ static int powerled_close(FAR struct file *filep) /* Free the IRQ and disable the POWERLED device */ - flags = enter_critical_section(); /* Disable interrupts */ + flags = enter_critical_section(); /* Disable interrupts */ dev->ops->shutdown(dev); /* Disable the POWERLED */ leave_critical_section(flags); @@ -189,7 +192,9 @@ static int powerled_ioctl(FAR struct file *filep, int cmd, unsigned long arg) { case PWRIOC_START: { - /* Allow powerled start only when limits set and structure is locked */ + /* Allow powerled start only when limits set and structure is + * locked + */ if (powerled->limits.lock == false || powerled->limits.current <= 0) @@ -330,7 +335,8 @@ static int powerled_ioctl(FAR struct file *filep, int cmd, unsigned long arg) } if (params->brightness < 0.0 || params->brightness > 100.0 || - params->frequency < 0.0 || params->duty < 0.0 || params->duty > 100.0) + params->frequency < 0.0 || params->duty < 0.0 || + params->duty > 100.0) { pwrerr("ERROR: powerled invalid parameters %f %f %f\n", params->brightness, params->frequency, params->duty); diff --git a/drivers/power/smps.c b/drivers/power/smps.c index 61ae801..ecb7e97 100644 --- a/drivers/power/smps.c +++ b/drivers/power/smps.c @@ -48,7 +48,8 @@ static ssize_t smps_read(FAR struct file *filep, FAR char *buffer, size_t buflen); static ssize_t smps_write(FAR struct file *filep, FAR const char *buffer, size_t buflen); -static int smps_ioctl(FAR struct file *filep, int cmd, unsigned long arg); +static int smps_ioctl(FAR struct file *filep, int cmd, + unsigned long arg); /**************************************************************************** * Private Data @@ -93,8 +94,8 @@ static int smps_open(FAR struct file *filep) if (ret >= 0) { /* Increment the count of references to the device. If this the first - * time that the driver has been opened for this device, then initialize - * the device. + * time that the driver has been opened for this device, then + * initialize the device. */ tmp = dev->ocount + 1; @@ -106,7 +107,9 @@ static int smps_open(FAR struct file *filep) } else { - /* Check if this is the first time that the driver has been opened. */ + /* Check if this is the first time that the driver has been + * opened. + */ if (tmp == 1) { @@ -167,7 +170,7 @@ static int smps_close(FAR struct file *filep) /* Free the IRQ and disable the SMPS device */ - flags = enter_critical_section(); /* Disable interrupts */ + flags = enter_critical_section(); /* Disable interrupts */ dev->ops->shutdown(dev); /* Disable the SMPS */ leave_critical_section(flags); @@ -182,7 +185,8 @@ static int smps_close(FAR struct file *filep) * Name: smps_read ****************************************************************************/ -static ssize_t smps_read(FAR struct file *filep, FAR char *buffer, size_t buflen) +static ssize_t smps_read(FAR struct file *filep, FAR char *buffer, + size_t buflen) { return 1; } @@ -239,7 +243,9 @@ static int smps_ioctl(FAR struct file *filep, int cmd, unsigned long arg) goto errout; } - /* When constan current mode, then output current must be provided */ + /* When constan current mode, then output current must be + * provided + */ if (smps->opmode == SMPS_OPMODE_CC && smps->param.i_out <= 0) { @@ -249,7 +255,9 @@ static int smps_ioctl(FAR struct file *filep, int cmd, unsigned long arg) goto errout; } - /* When constan voltage mode, then output voltage must be provided */ + /* When constan voltage mode, then output voltage must be + * provided + */ if (smps->opmode == SMPS_OPMODE_CV && smps->param.v_out <= 0) { @@ -462,7 +470,8 @@ errout: * Name: smps_register ****************************************************************************/ -int smps_register(FAR const char *path, FAR struct smps_dev_s *dev, FAR void *lower) +int smps_register(FAR const char *path, FAR struct smps_dev_s *dev, + FAR void *lower) { int ret; diff --git a/drivers/wireless/lpwan/sx127x/sx127x.h b/drivers/wireless/lpwan/sx127x/sx127x.h index 054de31..7cb3806 100644 --- a/drivers/wireless/lpwan/sx127x/sx127x.h +++ b/drivers/wireless/lpwan/sx127x/sx127x.h @@ -159,7 +159,7 @@ /* Operating mode & LORA/FSK selection */ -#define SX127X_CMN_OPMODE_MODE_SHIFT (0) /* Bits 0-2: Transceiver mode */ +#define SX127X_CMN_OPMODE_MODE_SHIFT (0) /* Bits 0-2: Transceiver mode */ #define SX127X_CMN_OPMODE_MODE_MASK (7 << SX127X_CMN_OPMODE_MODE_SHIFT) # define SX127X_CMN_OPMODE_MODE_SLEEP (0 << SX127X_CMN_OPMODE_MODE_SHIFT) /* SLEEP */ # define SX127X_CMN_OPMODE_MODE_STBY (1 << SX127X_CMN_OPMODE_MODE_SHIFT) /* STDBY */ @@ -169,12 +169,12 @@ # define SX127X_CMN_OPMODE_MODE_RX (5 << SX127X_CMN_OPMODE_MODE_SHIFT) /* RX in FSK/OOK, RXCONTINOUS in LORA */ # define SX127X_CMN_OPMODE_MODE_RXSINGLE (6 << SX127X_CMN_OPMODE_MODE_SHIFT) /* RXSINGLE (only LORA) */ # define SX127X_CMN_OPMODE_MODE_CAD (7 << SX127X_CMN_OPMODE_MODE_SHIFT) /* CAD (only LORA) */ -#define SX127X_CMN_OPMODE_LFMODEON (1 << 3) /* Bit 3: Low Frequency Mode ON */ -#define SX127X_CMN_OPMODE_MODTYPE_SHIFT (5) /* Bits 5-6: Modulation type (only FSK/OOK) */ +#define SX127X_CMN_OPMODE_LFMODEON (1 << 3) /* Bit 3: Low Frequency Mode ON */ +#define SX127X_CMN_OPMODE_MODTYPE_SHIFT (5) /* Bits 5-6: Modulation type (only FSK/OOK) */ # define SX127X_CMN_OPMODE_MODTYPE_MASK (3 << SX127X_CMN_OPMODE_MODTYPE_SHIFT) # define SX127X_CMN_OPMODE_MODTYPE_FSK (0 << SX127X_CMN_OPMODE_MODTYPE_SHIFT) # define SX127X_CMN_OPMODE_MODTYPE_OOK (1 << SX127X_CMN_OPMODE_MODTYPE_SHIFT) -#define SX127X_CMN_OPMODE_LRMODE (1 << 7) /* Bit 7: Long Range Mode 0-FSK/OOK, 1-LORA */ +#define SX127X_CMN_OPMODE_LRMODE (1 << 7) /* Bit 7: Long Range Mode 0-FSK/OOK, 1-LORA */ /* FSK/OOK/LORA: RF carrier frequency */ @@ -341,17 +341,17 @@ /* FSK/OOK: AFC, AGC, ctrl */ -#define SX127X_FOM_RXCFG_TRG_SHIFT (0) /* Bits 0-2: RX trigger */ +#define SX127X_FOM_RXCFG_TRG_SHIFT (0) /* Bits 0-2: RX trigger */ #define SX127X_FOM_RXCFG_TRG_MASK (7 << SX127X_FOM_RXCFG_TRG_SHIFT) # define SX127X_FOM_RXCFG_TRG_NONE (0 << SX127X_FOM_RXCFG_TRG_SHIFT) /* 000: */ # define SX127X_FOM_RXCFG_TRG_RSSI (1 << SX127X_FOM_RXCFG_TRG_SHIFT) /* 001: */ # define SX127X_FOM_RXCFG_TRG_PREDET (6 << SX127X_FOM_RXCFG_TRG_SHIFT) /* 110: */ # define SX127X_FOM_RXCFG_TRG_RSSIPREDET (7 << SX127X_FOM_RXCFG_TRG_SHIFT) /* 111: */ -#define SX127X_FOM_RXCFG_AGCAUTOON (1 << 3) /* Bit 3: AGC auto ON */ -#define SX127X_FOM_RXCFG_AFCAUTOON (1 << 4) /* Bit 4: AFC auto ON */ -#define SX127X_FOM_RXCFG_RESRXWITHPLL (1 << 5) /* Bit 5: Restar RX with PLL lock */ -#define SX127X_FOM_RXCFG_RESRXWITHOUTPLL (1 << 6) /* Bit 6: Restart RX without PLL lock */ -#define SX127X_FOM_RXCFG_RESRXONCOLLSION (1 << 7) /* Bit 7: Restart RX on collision */ +#define SX127X_FOM_RXCFG_AGCAUTOON (1 << 3) /* Bit 3: AGC auto ON */ +#define SX127X_FOM_RXCFG_AFCAUTOON (1 << 4) /* Bit 4: AFC auto ON */ +#define SX127X_FOM_RXCFG_RESRXWITHPLL (1 << 5) /* Bit 5: Restar RX with PLL lock */ +#define SX127X_FOM_RXCFG_RESRXWITHOUTPLL (1 << 6) /* Bit 6: Restart RX without PLL lock */ +#define SX127X_FOM_RXCFG_RESRXONCOLLSION (1 << 7) /* Bit 7: Restart RX on collision */ /* FSK/OOK: RSSI */ @@ -385,7 +385,6 @@ #define FSKOOK_BANDWIDTH_GET(mant, exp) (((exp << SX127X_FOM_RXBW_EXP_SHIFT) & SX127X_FOM_RXBW_EXP_MASK) | \ ((mant << SX127X_FOM_RXBW_MANT_SHIFT) & SX127X_FOM_RXBW_MANT_MASK)) - /* FSK/OOK: AFC Channel Filter BW */ #define SX127X_FOM_AFCBW_EXP_SHIFT (0) /* Bits 0-2: AFC exp */ @@ -509,20 +508,20 @@ /* FSK/OOK: Packet mode settings 1 */ -#define SX127X_FOM_PKTCFG1_CRCTYPE (1 << 0) /* Bit 0: CRC type: 0 -> CCITT CRC, 1 -> IBM CRC with alternate whitening */ -#define SX127X_FOM_PKTCFG1_ADDRFLT_SHIFT (1) /* Bits 1-2: Address basef filtering in RX */ +#define SX127X_FOM_PKTCFG1_CRCTYPE (1 << 0) /* Bit 0: CRC type: 0 -> CCITT CRC, 1 -> IBM CRC with alternate whitening */ +#define SX127X_FOM_PKTCFG1_ADDRFLT_SHIFT (1) /* Bits 1-2: Address basef filtering in RX */ #define SX127X_FOM_PKTCFG1_ADDRFLT_MASK (3 << SX127X_FOM_PKTCFG1_ADDRFLT_SHIFT) # define SX127X_FOM_PKTCFG1_ADDRFLT_OFF (0 << SX127X_FOM_PKTCFG1_ADDRFLT_SHIFT) # define SX127X_FOM_PKTCFG1_ADDRFLT_NA (1 << SX127X_FOM_PKTCFG1_ADDRFLT_SHIFT) # define SX127X_FOM_PKTCFG1_ADDRFLT_NABA (2 << SX127X_FOM_PKTCFG1_ADDRFLT_SHIFT) -#define SX127X_FOM_PKTCFG1_CRCAUTOCLROFF (1 << 3) /* Bit 3: CRC auto clear OFF */ -#define SX127X_FOM_PKTCFG1_CRCON (1 << 4) /* Bit 4: TX/RX CRC enable */ -#define SX127X_FOM_PKTCFG1_DCFREE_SHIFT (5) /* Bits 5-6: DC-free encodeing/decoding */ +#define SX127X_FOM_PKTCFG1_CRCAUTOCLROFF (1 << 3) /* Bit 3: CRC auto clear OFF */ +#define SX127X_FOM_PKTCFG1_CRCON (1 << 4) /* Bit 4: TX/RX CRC enable */ +#define SX127X_FOM_PKTCFG1_DCFREE_SHIFT (5) /* Bits 5-6: DC-free encodeing/decoding */ #define SX127X_FOM_PKTCFG1_DCFREE_MASK (3 << SX127X_FOM_PKTCFG1_DCFREE_SHIFT) # define SX127X_FOM_PKTCFG1_DCFREE_OFF (0 << SX127X_FOM_PKTCFG1_DCFREE_SHIFT) /* 00: None */ # define SX127X_FOM_PKTCFG1_DCFREE_M (1 << SX127X_FOM_PKTCFG1_DCFREE_SHIFT) /* 01: Manchaster */ # define SX127X_FOM_PKTCFG1_DCFREE_W (2 << SX127X_FOM_PKTCFG1_DCFREE_SHIFT) /* 10: Whitening */ -#define SX127X_FOM_PKTCFG1_PCKFORMAT (1 << 7) /* Bit 7: 0 -> fixed length, 1 -> variable length*/ +#define SX127X_FOM_PKTCFG1_PCKFORMAT (1 << 7) /* Bit 7: 0 -> fixed length, 1 -> variable length*/ /* FSK/OOK: Packet mode settings 2 */ @@ -547,18 +546,18 @@ /* FSK/OOK: Top level Sequencer settings 1 */ -#define SX127X_FOM_SEQCFG1_TX (1 << 0) /* Bit 0: From Transmit 0 -> LowPowerSelection, 1 -> Receive */ -#define SX127X_FOM_SEQCFG1_IDLE (1 << 1) /* Bit 1: From IDLE on T1: 0 -> TX, 1 -> RX*/ -#define SX127X_FOM_SEQCFG1_LOWPOWERSEL (1 << 2) /* Bit 2: Low Power Selection */ -#define SX127X_FOM_SEQCFG1_START_SHIFT (3) /* Bits 3-4: From Start */ +#define SX127X_FOM_SEQCFG1_TX (1 << 0) /* Bit 0: From Transmit 0 -> LowPowerSelection, 1 -> Receive */ +#define SX127X_FOM_SEQCFG1_IDLE (1 << 1) /* Bit 1: From IDLE on T1: 0 -> TX, 1 -> RX*/ +#define SX127X_FOM_SEQCFG1_LOWPOWERSEL (1 << 2) /* Bit 2: Low Power Selection */ +#define SX127X_FOM_SEQCFG1_START_SHIFT (3) /* Bits 3-4: From Start */ #define SX127X_FOM_SEQCFG1_START_MASK (3 << SX127X_FOM_SEQCFG1_START_SHIFT) # define SX127X_FOM_SEQCFG1_START_LPS (0 << SX127X_FOM_SEQCFG1_START_SHIFT) /* LowPowerSelection */ # define SX127X_FOM_SEQCFG1_START_RS (1 << SX127X_FOM_SEQCFG1_START_SHIFT) /* RX */ # define SX127X_FOM_SEQCFG1_START_TS (2 << SX127X_FOM_SEQCFG1_START_SHIFT) /* TX */ # define SX127X_FOM_SEQCFG1_START_TSFL (3 << SX127X_FOM_SEQCFG1_START_SHIFT) /* TX on FifoLevel */ -#define SX127X_FOM_SEQCFG1_IDLEMODE (1 << 5) /* Bit 5: IDLE Mode 0 -> standby, 1 -> sleep */ -#define SX127X_FOM_SEQCFG1_SEQSTOP (1 << 6) /* Bit 6: Sequencer Stop */ -#define SX127X_FOM_SEQCFG1_SEQSTART (1 << 7) /* Bit 7: Sequencer Start */ +#define SX127X_FOM_SEQCFG1_IDLEMODE (1 << 5) /* Bit 5: IDLE Mode 0 -> standby, 1 -> sleep */ +#define SX127X_FOM_SEQCFG1_SEQSTOP (1 << 6) /* Bit 6: Sequencer Stop */ +#define SX127X_FOM_SEQCFG1_SEQSTART (1 << 7) /* Bit 7: Sequencer Start */ /* FSK/OOK: Top level Sequencer settings 2 */ @@ -803,7 +802,7 @@ #define LORA_DATARATE_GET(sf, bw, cr) (sf * bw * cr / (2<<sf)) -/* Constants ***************************************************************/ +/* Constants ****************************************************************/ /* FXOSC is 32 MHz */ @@ -827,7 +826,7 @@ #endif /**************************************************************************** - * Public Functions + * Public Functions Prototypes ****************************************************************************/ #undef EXTERN diff --git a/include/nuttx/power/motor.h b/include/nuttx/power/motor.h index 396eb43..d267485 100644 --- a/include/nuttx/power/motor.h +++ b/include/nuttx/power/motor.h @@ -21,11 +21,10 @@ #ifndef __INCLUDE_NUTTX_DRIVERS_POWER_MOTOR_H #define __INCLUDE_NUTTX_DRIVERS_POWER_MOTOR_H -/* - * The motor driver is split into two parts: +/* The motor driver is split into two parts: * - * 1) An "upper half", generic driver that provides the common motor interface - * to application level code, and + * 1) An "upper half", generic driver that provides the common motor + * interface to application level code, and * 2) A "lower half", platform-specific driver that implements the low-level * functionality eg.: * - timer controls to implement the PWM signals, @@ -200,7 +199,7 @@ struct motor_params_s float speed; /* Motor speed */ #endif #ifdef CONFIG_MOTOR_HAVE_TORQUE - float torque; /* Motor torque (rotary motor)*/ + float torque; /* Motor torque (rotary motor) */ #endif #ifdef CONFIG_MOTOR_HAVE_FORCE float force; /* Motor force (linear motor) */ diff --git a/include/nuttx/power/powerled.h b/include/nuttx/power/powerled.h index a8b8442..34a9bcd 100644 --- a/include/nuttx/power/powerled.h +++ b/include/nuttx/power/powerled.h @@ -21,8 +21,7 @@ #ifndef __INCLUDE_NUTTX_DRIVERS_POWER_POWERLED_H #define __INCLUDE_NUTTX_DRIVERS_POWER_POWERLED_H -/* - * The powerled driver is split into two parts: +/* The powerled driver is split into two parts: * * 1) An "upper half", generic driver that provides the common high power LED * interface to application level code, and @@ -80,7 +79,7 @@ enum powerled_state_e enum powerled_fault_e { - POWERLED_FAULT_OVERHEAT = (1<<0) /* Overheat fault */ + POWERLED_FAULT_OVERHEAT = (1 << 0) /* Overheat fault */ }; /* This structure describes converter state */ @@ -98,7 +97,7 @@ struct powerled_limits_s bool lock; /* This bit must be set after * limits configuration. */ - float current; /* Max current for LED */ + float current; /* Max current for LED */ }; /* Powerled parameters */ @@ -131,8 +130,8 @@ struct powerled_s FAR void *priv; /* Private data */ }; -/* Powerled operations used to call from the upper-half, generic powerled driver - * into lower-half, platform-specific logic. +/* Powerled operations used to call from the upper-half, generic powerled + * driver into lower-half, platform-specific logic. */ struct powerled_dev_s; @@ -187,12 +186,14 @@ struct powerled_ops_s /* Lower-half logic may support platform-specific ioctl commands */ - CODE int (*ioctl)(FAR struct powerled_dev_s *dev, int cmd, unsigned long arg); + CODE int (*ioctl)(FAR struct powerled_dev_s *dev, int cmd, + unsigned long arg); }; -/* Powerled device structure used by the driver. The caller of powerled_register - * must allocate and initialize this structure. The calling logic need - * provide 'ops', 'priv' and 'lower' elements. +/* Powerled device structure used by the driver. + * The caller of powerled_register must allocate and initialize this + * structure. The calling logic need provide 'ops', 'priv' and 'lower' + * elements. */ struct powerled_dev_s @@ -202,7 +203,7 @@ struct powerled_dev_s uint8_t ocount; /* The number of times the device * has been opened */ - sem_t closesem; /* Locks out new opens while close + sem_t closesem; /* Locks out new opens while close * is in progress */ diff --git a/include/nuttx/power/smps.h b/include/nuttx/power/smps.h index 333621a..a1c2917 100644 --- a/include/nuttx/power/smps.h +++ b/include/nuttx/power/smps.h @@ -21,8 +21,7 @@ #ifndef __INCLUDE_NUTTX_DRIVERS_POWER_SMPS_H #define __INCLUDE_NUTTX_DRIVERS_POWER_SMPS_H -/* - * The SMPS (switched-mode power supply) driver is split into two parts: +/* The SMPS (switched-mode power supply) driver is split into two parts: * * 1) An "upper half", generic driver that provides the common SMPS interface * to application level code, and @@ -65,7 +64,7 @@ enum smps_opmode_e SMPS_OPMODE_INIT = 0, /* Initial mode */ SMPS_OPMODE_CC = 1, /* Constant current mode */ SMPS_OPMODE_CV = 2, /* Constant voltage mode */ - SMPS_OPMODE_CP = 3 /* Constant power mode*/ + SMPS_OPMODE_CP = 3 /* Constant power mode */ }; /* SMPS state */ diff --git a/include/nuttx/wireless/lpwan/sx127x.h b/include/nuttx/wireless/lpwan/sx127x.h index f626763..3d649cf 100644 --- a/include/nuttx/wireless/lpwan/sx127x.h +++ b/include/nuttx/wireless/lpwan/sx127x.h @@ -289,7 +289,7 @@ struct sx127x_lower_s }; /**************************************************************************** - * Public Functions + * Public Functions Prototypes ****************************************************************************/ int sx127x_register(FAR struct spi_dev_s *spi, diff --git a/libs/libdsp/lib_foc.c b/libs/libdsp/lib_foc.c index 10a3170..0f93106 100644 --- a/libs/libdsp/lib_foc.c +++ b/libs/libdsp/lib_foc.c @@ -258,7 +258,9 @@ void foc_process(FAR struct foc_data_s *foc, inv_park_transform(angle, &foc->v_dq, &foc->v_ab); - /* Normalize the alpha-beta voltage to get the alpha-beta modulation voltage */ + /* Normalize the alpha-beta voltage to get the alpha-beta modulation + * voltage + */ foc->v_ab_mod.a = foc->v_ab.a * foc->vab_mod_scale; foc->v_ab_mod.b = foc->v_ab.b * foc->vab_mod_scale;
