v01d commented on pull request #2189:
URL: https://github.com/apache/incubator-nuttx/pull/2189#issuecomment-721414608
Here's the patch with changes so far. I can't figure how this broke, can't
find anything else wrong.
Reverting this PR (and applying a hacky approach to not define MISO) works
as expected.
```
diff --git a/arch/arm/src/nrf52/hardware/nrf52_spi.h
b/arch/arm/src/nrf52/hardware/nrf52_spi.h
index 9a983612e7..b2d0062c75 100644
--- a/arch/arm/src/nrf52/hardware/nrf52_spi.h
+++ b/arch/arm/src/nrf52/hardware/nrf52_spi.h
@@ -159,7 +159,7 @@
#define SPIM_PSEL_PIN_MASK (0x1f << SPIM_PSEL_PIN_SHIFT)
#define SPIM_PSEL_PORT_SHIFT (5) /* Bit 5: port number */
#define SPIM_PSEL_PORT_MASK (0x1 << SPIM_PSEL_PORT_SHIFT)
-#define SPIM_PSEL_CONNECTED (1 << 31) /* Bit 31: Connection */
+#define SPIM_PSEL_DISCONNECTED (1 << 31) /* Bit 31: Disconnected */
#define SPIM_PSEL_RESET (0xffffffff)
/* FREQUENCY Register */
diff --git a/arch/arm/src/nrf52/nrf52_spi.c b/arch/arm/src/nrf52/nrf52_spi.c
index afc275c812..d29fbee11c 100644
--- a/arch/arm/src/nrf52/nrf52_spi.c
+++ b/arch/arm/src/nrf52/nrf52_spi.c
@@ -414,12 +414,13 @@ static int nrf52_spi_isr(int irq, FAR void *context,
FAR void *arg)
static void nrf52_spi_pselinit(uint32_t pselreg, nrf52_pinset_t pinset)
{
- uint32_t regval;
+ uint32_t regval = 0;
int pin = GPIO_PIN_DECODE(pinset);
int port = GPIO_PORT_DECODE(pinset);
regval = (pin << SPIM_PSEL_PIN_SHIFT);
regval |= (port << SPIM_PSEL_PORT_SHIFT);
+
putreg32(pselreg, regval);
}
@@ -443,12 +444,12 @@ static void nrf52_spi_gpioinit(FAR struct
nrf52_spidev_s *priv)
nrf52_gpio_config(BOARD_SPI0_MISO_PIN);
nrf52_spi_pselinit(priv->base + NRF52_SPIM_PSELMISO_OFFSET,
BOARD_SPI0_MISO_PIN);
- nrf52_gpio_write(BOARD_SPI0_MISO_PIN, false);
#endif
#ifdef BOARD_SPI0_MOSI_PIN
nrf52_gpio_config(BOARD_SPI0_MOSI_PIN);
nrf52_spi_pselinit(priv->base + NRF52_SPIM_PSELMOSI_OFFSET,
BOARD_SPI0_MOSI_PIN);
+ nrf52_gpio_write(BOARD_SPI0_MOSI_PIN, false);
#endif
}
#endif
@@ -460,12 +461,12 @@ static void nrf52_spi_gpioinit(FAR struct
nrf52_spidev_s *priv)
nrf52_gpio_config(BOARD_SPI1_MISO_PIN);
nrf52_spi_pselinit(priv->base + NRF52_SPIM_PSELMISO_OFFSET,
BOARD_SPI1_MISO_PIN);
- nrf52_gpio_write(BOARD_SPI1_MISO_PIN, false);
#endif
#ifdef BOARD_SPI1_MOSI_PIN
nrf52_gpio_config(BOARD_SPI1_MOSI_PIN);
nrf52_spi_pselinit(priv->base + NRF52_SPIM_PSELMOSI_OFFSET,
BOARD_SPI1_MOSI_PIN);
+ nrf52_gpio_write(BOARD_SPI1_MOSI_PIN, false);
#endif
}
#endif
@@ -476,13 +477,13 @@ static void nrf52_spi_gpioinit(FAR struct
nrf52_spidev_s *priv)
#ifdef BOARD_SPI2_MISO_PIN
nrf52_gpio_config(BOARD_SPI2_MISO_PIN);
nrf52_spi_pselinit(priv->base + NRF52_SPIM_PSELMISO_OFFSET,
- BOARD_SPI1_MISO_PIN);
- nrf52_gpio_write(BOARD_SPI1_MISO_PIN, false);
+ BOARD_SPI2_MISO_PIN);
#endif
#ifdef BOARD_SPI2_MOSI_PIN
nrf52_gpio_config(BOARD_SPI2_MOSI_PIN);
nrf52_spi_pselinit(priv->base + NRF52_SPIM_PSELMOSI_OFFSET,
BOARD_SPI2_MOSI_PIN);
+ nrf52_gpio_write(BOARD_SPI2_MOSI_PIN, false);
#endif
}
#endif
@@ -494,12 +495,12 @@ static void nrf52_spi_gpioinit(FAR struct
nrf52_spidev_s *priv)
nrf52_gpio_config(BOARD_SPI3_MISO_PIN);
nrf52_spi_pselinit(priv->base + NRF52_SPIM_PSELMISO_OFFSET,
BOARD_SPI3_MISO_PIN);
- nrf52_gpio_write(BOARD_SPI1_MISO_PIN, false);
#endif
#ifdef BOARD_SPI3_MOSI_PIN
nrf52_gpio_config(BOARD_SPI3_MOSI_PIN);
nrf52_spi_pselinit(priv->base + NRF52_SPIM_PSELMOSI_OFFSET,
BOARD_SPI3_MOSI_PIN);
+ nrf52_gpio_write(BOARD_SPI3_MOSI_PIN, false);
#endif
}
#endif
@@ -870,14 +871,16 @@ static uint32_t nrf52_spi_send(FAR struct spi_dev_s
*dev, uint32_t wd)
*
****************************************************************************/
+#include "nrf52_gpiote.h"
+
static void nrf52_spi_1b_workaround(FAR struct spi_dev_s *dev, bool enable)
{
FAR struct nrf52_spidev_s *priv = (FAR struct nrf52_spidev_s *)dev;
uint32_t pin = 0;
uint32_t port = 0;
- pin = (priv->sck_pin & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
- port = (priv->sck_pin & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
+ pin = GPIO_PIN_DECODE(priv->sck_pin);
+ port = GPIO_PORT_DECODE(priv->sck_pin);
if (enable == true)
{
```
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