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The following commit(s) were added to refs/heads/master by this push:
new 6547c3d arch/riscv: Fix file names in headers that were still using
the old 'up_' prefix.
6547c3d is described below
commit 6547c3df55339db2c3ba71a3fc9d4d8d9420210c
Author: Abdelatif Guettouche <[email protected]>
AuthorDate: Fri Feb 5 23:04:20 2021 +0100
arch/riscv: Fix file names in headers that were still using the old 'up_'
prefix.
Signed-off-by: Abdelatif Guettouche <[email protected]>
---
arch/risc-v/src/rv32im/riscv_assert.c | 2 +-
arch/risc-v/src/rv32im/riscv_blocktask.c | 2 +-
arch/risc-v/src/rv32im/riscv_copystate.c | 2 +-
arch/risc-v/src/rv32im/riscv_doirq.c | 2 +-
arch/risc-v/src/rv32im/riscv_fpu.S | 2 +-
arch/risc-v/src/rv32im/riscv_initialstate.c | 2 +-
arch/risc-v/src/rv32im/riscv_releasepending.c | 2 +-
arch/risc-v/src/rv32im/riscv_reprioritizertr.c | 2 +-
arch/risc-v/src/rv32im/riscv_sigdeliver.c | 2 +-
arch/risc-v/src/rv32im/riscv_syscall.S | 2 +-
arch/risc-v/src/rv32im/riscv_unblocktask.c | 2 +-
arch/risc-v/src/rv64gc/riscv_assert.c | 2 +-
arch/risc-v/src/rv64gc/riscv_blocktask.c | 2 +-
arch/risc-v/src/rv64gc/riscv_copystate.c | 2 +-
arch/risc-v/src/rv64gc/riscv_fault.c | 2 +-
arch/risc-v/src/rv64gc/riscv_initialstate.c | 2 +-
arch/risc-v/src/rv64gc/riscv_releasepending.c | 2 +-
arch/risc-v/src/rv64gc/riscv_reprioritizertr.c | 2 +-
arch/risc-v/src/rv64gc/riscv_sigdeliver.c | 2 +-
arch/risc-v/src/rv64gc/riscv_signal_dispatch.c | 2 +-
arch/risc-v/src/rv64gc/riscv_signal_handler.S | 2 +-
arch/risc-v/src/rv64gc/riscv_swint.c | 2 +-
arch/risc-v/src/rv64gc/riscv_testset.S | 2 +-
arch/risc-v/src/rv64gc/riscv_unblocktask.c | 2 +-
24 files changed, 24 insertions(+), 24 deletions(-)
diff --git a/arch/risc-v/src/rv32im/riscv_assert.c
b/arch/risc-v/src/rv32im/riscv_assert.c
index 2dfe3c5..736c9fb 100644
--- a/arch/risc-v/src/rv32im/riscv_assert.c
+++ b/arch/risc-v/src/rv32im/riscv_assert.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/rv32im/up_assert.c
+ * arch/risc-v/src/rv32im/riscv_assert.c
*
* Copyright (C) 2011-2015, 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <[email protected]>
diff --git a/arch/risc-v/src/rv32im/riscv_blocktask.c
b/arch/risc-v/src/rv32im/riscv_blocktask.c
index 2b14183..6f5df0e 100644
--- a/arch/risc-v/src/rv32im/riscv_blocktask.c
+++ b/arch/risc-v/src/rv32im/riscv_blocktask.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/rv32im/up_blocktask.c
+ * arch/risc-v/src/rv32im/riscv_blocktask.c
*
* Copyright (C) 2011, 2013-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <[email protected]>
diff --git a/arch/risc-v/src/rv32im/riscv_copystate.c
b/arch/risc-v/src/rv32im/riscv_copystate.c
index caec942..66e734a 100644
--- a/arch/risc-v/src/rv32im/riscv_copystate.c
+++ b/arch/risc-v/src/rv32im/riscv_copystate.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/rv32im/up_copystate.c
+ * arch/risc-v/src/rv32im/riscv_copystate.c
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <[email protected]>
diff --git a/arch/risc-v/src/rv32im/riscv_doirq.c
b/arch/risc-v/src/rv32im/riscv_doirq.c
index 77ce6b9..fc97027 100644
--- a/arch/risc-v/src/rv32im/riscv_doirq.c
+++ b/arch/risc-v/src/rv32im/riscv_doirq.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/rv32im/up_doirq.c
+ * arch/risc-v/src/rv32im/riscv_doirq.c
*
* Copyright (C) 2011, 2014-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <[email protected]>
diff --git a/arch/risc-v/src/rv32im/riscv_fpu.S
b/arch/risc-v/src/rv32im/riscv_fpu.S
index f2a9766..a4e3902 100644
--- a/arch/risc-v/src/rv32im/riscv_fpu.S
+++ b/arch/risc-v/src/rv32im/riscv_fpu.S
@@ -1,5 +1,5 @@
/************************************************************************************
- * arch/risc-v/src/rv32im/up_fpu.S
+ * arch/risc-v/src/rv32im/riscv_fpu.S
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
diff --git a/arch/risc-v/src/rv32im/riscv_initialstate.c
b/arch/risc-v/src/rv32im/riscv_initialstate.c
index 8c59d63..4723dea 100644
--- a/arch/risc-v/src/rv32im/riscv_initialstate.c
+++ b/arch/risc-v/src/rv32im/riscv_initialstate.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/rv32im/up_initialstate.c
+ * arch/risc-v/src/rv32im/riscv_initialstate.c
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <[email protected]>
diff --git a/arch/risc-v/src/rv32im/riscv_releasepending.c
b/arch/risc-v/src/rv32im/riscv_releasepending.c
index d8c0de1..3f992c6 100644
--- a/arch/risc-v/src/rv32im/riscv_releasepending.c
+++ b/arch/risc-v/src/rv32im/riscv_releasepending.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/rv32im/up_releasepending.c
+ * arch/risc-v/src/rv32im/riscv_releasepending.c
*
* Copyright (C) 2011, 2014-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <[email protected]>
diff --git a/arch/risc-v/src/rv32im/riscv_reprioritizertr.c
b/arch/risc-v/src/rv32im/riscv_reprioritizertr.c
index 4c42e58..11b073e 100644
--- a/arch/risc-v/src/rv32im/riscv_reprioritizertr.c
+++ b/arch/risc-v/src/rv32im/riscv_reprioritizertr.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/rv32im/up_reprioritizertr.c
+ * arch/risc-v/src/rv32im/riscv_reprioritizertr.c
*
* Copyright (C) 2011, 2013-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <[email protected]>
diff --git a/arch/risc-v/src/rv32im/riscv_sigdeliver.c
b/arch/risc-v/src/rv32im/riscv_sigdeliver.c
index cdb2741..b48d75c 100644
--- a/arch/risc-v/src/rv32im/riscv_sigdeliver.c
+++ b/arch/risc-v/src/rv32im/riscv_sigdeliver.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/rv32im/up_sigdeliver.c
+ * arch/risc-v/src/rv32im/riscv_sigdeliver.c
*
* Copyright (C) 2011, 2015, 2018-2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <[email protected]>
diff --git a/arch/risc-v/src/rv32im/riscv_syscall.S
b/arch/risc-v/src/rv32im/riscv_syscall.S
index 5545fa7..52e69ec 100644
--- a/arch/risc-v/src/rv32im/riscv_syscall.S
+++ b/arch/risc-v/src/rv32im/riscv_syscall.S
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/riscv/src/rv32im/up_syscall.S
+ * arch/riscv/src/rv32im/riscv_syscall.S
*
* Copyright (C) 2011, 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <[email protected]>
diff --git a/arch/risc-v/src/rv32im/riscv_unblocktask.c
b/arch/risc-v/src/rv32im/riscv_unblocktask.c
index 3b67cf8..69c8c6e 100644
--- a/arch/risc-v/src/rv32im/riscv_unblocktask.c
+++ b/arch/risc-v/src/rv32im/riscv_unblocktask.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/rv32im/up_unblocktask.c
+ * arch/risc-v/src/rv32im/riscv_unblocktask.c
*
* Copyright (C) 2011, 2013-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <[email protected]>
diff --git a/arch/risc-v/src/rv64gc/riscv_assert.c
b/arch/risc-v/src/rv64gc/riscv_assert.c
index 67071da..161326a 100644
--- a/arch/risc-v/src/rv64gc/riscv_assert.c
+++ b/arch/risc-v/src/rv64gc/riscv_assert.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/rv64gc/up_assert.c
+ * arch/risc-v/src/rv64gc/riscv_assert.c
*
* Copyright (C) 2011-2015, 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <[email protected]>
diff --git a/arch/risc-v/src/rv64gc/riscv_blocktask.c
b/arch/risc-v/src/rv64gc/riscv_blocktask.c
index 24b98ca..63bed2c 100644
--- a/arch/risc-v/src/rv64gc/riscv_blocktask.c
+++ b/arch/risc-v/src/rv64gc/riscv_blocktask.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/rv64gc/up_blocktask.c
+ * arch/risc-v/src/rv64gc/riscv_blocktask.c
*
* Copyright (C) 2011, 2013-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <[email protected]>
diff --git a/arch/risc-v/src/rv64gc/riscv_copystate.c
b/arch/risc-v/src/rv64gc/riscv_copystate.c
index 8b8fe6d..37df1b8 100644
--- a/arch/risc-v/src/rv64gc/riscv_copystate.c
+++ b/arch/risc-v/src/rv64gc/riscv_copystate.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/rv64gc/up_copystate.c
+ * arch/risc-v/src/rv64gc/riscv_copystate.c
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <[email protected]>
diff --git a/arch/risc-v/src/rv64gc/riscv_fault.c
b/arch/risc-v/src/rv64gc/riscv_fault.c
index d60710f..1b18e31 100644
--- a/arch/risc-v/src/rv64gc/riscv_fault.c
+++ b/arch/risc-v/src/rv64gc/riscv_fault.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/rv64gc/up_fault.c
+ * arch/risc-v/src/rv64gc/riscv_fault.c
*
* Copyright (C) 2020 Masayuki Ishikawa. All rights reserved.
* Author: Masayuki Ishikawa <[email protected]>
diff --git a/arch/risc-v/src/rv64gc/riscv_initialstate.c
b/arch/risc-v/src/rv64gc/riscv_initialstate.c
index 2fd4913..c92f31e 100644
--- a/arch/risc-v/src/rv64gc/riscv_initialstate.c
+++ b/arch/risc-v/src/rv64gc/riscv_initialstate.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/rv64gc/up_initialstate.c
+ * arch/risc-v/src/rv64gc/riscv_initialstate.c
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <[email protected]>
diff --git a/arch/risc-v/src/rv64gc/riscv_releasepending.c
b/arch/risc-v/src/rv64gc/riscv_releasepending.c
index eff977c..2663e22 100644
--- a/arch/risc-v/src/rv64gc/riscv_releasepending.c
+++ b/arch/risc-v/src/rv64gc/riscv_releasepending.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/rv64gc/up_releasepending.c
+ * arch/risc-v/src/rv64gc/riscv_releasepending.c
*
* Copyright (C) 2011, 2014-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <[email protected]>
diff --git a/arch/risc-v/src/rv64gc/riscv_reprioritizertr.c
b/arch/risc-v/src/rv64gc/riscv_reprioritizertr.c
index a415766..e268de8 100644
--- a/arch/risc-v/src/rv64gc/riscv_reprioritizertr.c
+++ b/arch/risc-v/src/rv64gc/riscv_reprioritizertr.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/rv64gc/up_reprioritizertr.c
+ * arch/risc-v/src/rv64gc/riscv_reprioritizertr.c
*
* Copyright (C) 2011, 2013-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <[email protected]>
diff --git a/arch/risc-v/src/rv64gc/riscv_sigdeliver.c
b/arch/risc-v/src/rv64gc/riscv_sigdeliver.c
index b08dff1..f773bee 100644
--- a/arch/risc-v/src/rv64gc/riscv_sigdeliver.c
+++ b/arch/risc-v/src/rv64gc/riscv_sigdeliver.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/rv64gc/up_sigdeliver.c
+ * arch/risc-v/src/rv64gc/riscv_sigdeliver.c
*
* Copyright (C) 2011, 2015, 2018-2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <[email protected]>
diff --git a/arch/risc-v/src/rv64gc/riscv_signal_dispatch.c
b/arch/risc-v/src/rv64gc/riscv_signal_dispatch.c
index 3dadf00..46f6670 100644
--- a/arch/risc-v/src/rv64gc/riscv_signal_dispatch.c
+++ b/arch/risc-v/src/rv64gc/riscv_signal_dispatch.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/rv64gc/up_signal_dispatch.c
+ * arch/risc-v/src/rv64gc/riscv_signal_dispatch.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
diff --git a/arch/risc-v/src/rv64gc/riscv_signal_handler.S
b/arch/risc-v/src/rv64gc/riscv_signal_handler.S
index 231dcc8..5317523 100644
--- a/arch/risc-v/src/rv64gc/riscv_signal_handler.S
+++ b/arch/risc-v/src/rv64gc/riscv_signal_handler.S
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/rv64gc/up_signal_handler.S
+ * arch/risc-v/src/rv64gc/riscv_signal_handler.S
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
diff --git a/arch/risc-v/src/rv64gc/riscv_swint.c
b/arch/risc-v/src/rv64gc/riscv_swint.c
index 8fe9435..45031dc 100644
--- a/arch/risc-v/src/rv64gc/riscv_swint.c
+++ b/arch/risc-v/src/rv64gc/riscv_swint.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/riscv/src/rv64gc/up_swint.c
+ * arch/riscv/src/rv64gc/riscv_swint.c
*
* Copyright (C) 2011-2012, 2015, 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <[email protected]>
diff --git a/arch/risc-v/src/rv64gc/riscv_testset.S
b/arch/risc-v/src/rv64gc/riscv_testset.S
index 688e445..8bff036 100644
--- a/arch/risc-v/src/rv64gc/riscv_testset.S
+++ b/arch/risc-v/src/rv64gc/riscv_testset.S
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/rv64gc/up_testset.S
+ * arch/risc-v/src/rv64gc/riscv_testset.S
*
* Copyright (C) 2020 Masayuki Ishikawa. All rights reserved.
* Author: Masayuki Ishikawa <[email protected]>
diff --git a/arch/risc-v/src/rv64gc/riscv_unblocktask.c
b/arch/risc-v/src/rv64gc/riscv_unblocktask.c
index 0dfd147..5f4d990 100644
--- a/arch/risc-v/src/rv64gc/riscv_unblocktask.c
+++ b/arch/risc-v/src/rv64gc/riscv_unblocktask.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/rv64gc/up_unblocktask.c
+ * arch/risc-v/src/rv64gc/riscv_unblocktask.c
*
* Copyright (C) 2011, 2013-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <[email protected]>
