This is an automated email from the ASF dual-hosted git repository.
jerpelea pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
The following commit(s) were added to refs/heads/master by this push:
new 13816de arch/stm32f7: Fix nxstyle errors
13816de is described below
commit 13816de7ac78af4c0e8eccdcfe3f7647adc0b0b6
Author: Nathan Hartman <59230071+hartmannat...@users.noreply.github.com>
AuthorDate: Mon Mar 15 09:46:27 2021 -0400
arch/stm32f7: Fix nxstyle errors
arch/arm/include/stm32f7/chip.h:
arch/arm/include/stm32f7/irq.h:
arch/arm/include/stm32f7/stm32f72xx73xx_irq.h:
arch/arm/include/stm32f7/stm32f74xx75xx_irq.h:
arch/arm/include/stm32f7/stm32f76xx77xx_irq.h:
* Fix nxstyle errors.
---
arch/arm/include/stm32f7/chip.h | 16 +-
arch/arm/include/stm32f7/irq.h | 40 ++--
arch/arm/include/stm32f7/stm32f72xx73xx_irq.h | 46 ++---
arch/arm/include/stm32f7/stm32f74xx75xx_irq.h | 40 ++--
arch/arm/include/stm32f7/stm32f76xx77xx_irq.h | 258 +++++++++++++-------------
5 files changed, 210 insertions(+), 190 deletions(-)
diff --git a/arch/arm/include/stm32f7/chip.h b/arch/arm/include/stm32f7/chip.h
index 1a31384..a77dae3 100644
--- a/arch/arm/include/stm32f7/chip.h
+++ b/arch/arm/include/stm32f7/chip.h
@@ -1,4 +1,4 @@
-/************************************************************************************
+/********************************************************************************************************************
* arch/arm/include/stm32f7/chip.h
*
* Copyright (C) 2015-2017 Gregory Nutt. All rights reserved.
@@ -33,20 +33,21 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
-
************************************************************************************/
+
********************************************************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_STM32F7_CHIP_H
#define __ARCH_ARM_INCLUDE_STM32F7_CHIP_H
-/************************************************************************************
+/********************************************************************************************************************
* Included Files
-
************************************************************************************/
+
********************************************************************************************************************/
#include <nuttx/config.h>
-/************************************************************************************
+/********************************************************************************************************************
* Pre-processor Definitions
-
************************************************************************************/
+
********************************************************************************************************************/
+
/* STM32F722xx, STM32F723xx,
* STM32F745xx, STM32F746xx, STM32F756xx, STM32F765xx, STM32F767xx,
STM32F768xx,
* STM32F769xx, STM32F777xx and STM32F779xx Differences between family
members:
@@ -373,7 +374,8 @@
#define STM32F7_NDFSDM 0 /* No Digital filters */
#endif
-/* NVIC priority levels
*************************************************************/
+/* NVIC priority levels
*********************************************************************************************/
+
/* 16 Programmable interrupt levels */
#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */
diff --git a/arch/arm/include/stm32f7/irq.h b/arch/arm/include/stm32f7/irq.h
index eb4042d..2147d54 100644
--- a/arch/arm/include/stm32f7/irq.h
+++ b/arch/arm/include/stm32f7/irq.h
@@ -1,4 +1,4 @@
-/************************************************************************************
+/****************************************************************************
* arch/arm/include/stm32f7/irq.h
*
* Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
@@ -32,7 +32,7 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
-
************************************************************************************/
+ ****************************************************************************/
/* This file should never be included directly but, rather,
* only indirectly through nuttx/irq.h
@@ -41,19 +41,19 @@
#ifndef __ARCH_ARM_INCLUDE_STM32F7_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32F7_IRQ_H
-/************************************************************************************
+/****************************************************************************
* Included Files
-
************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
-/************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
-
************************************************************************************/
+ ****************************************************************************/
-/* IRQ numbers. The IRQ number corresponds vector number and hence map
directly to
- * bits in the NVIC. This does, however, waste several words of memory in the
IRQ
- * to handle mapping tables.
+/* IRQ numbers. The IRQ number corresponds vector number and hence map
+ * directly to bits in the NVIC. This does, however, waste several words of
+ * memory in the IRQ to handle mapping tables.
*/
/* Processor Exceptions (vectors 0-15) */
@@ -73,10 +73,16 @@
#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service
request */
#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */
-/* External interrupts (vectors >= 16). These definitions are chip-specific */
+/* External interrupts (vectors >= 16).
+ * These definitions are chip-specific
+ */
#define STM32_IRQ_FIRST (16) /* Vector number of the first external
interrupt */
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
# include <arch/stm32f7/stm32f72xx73xx_irq.h>
#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
@@ -87,13 +93,13 @@
# error "Unsupported STM32 F7 chip"
#endif
-/************************************************************************************
+/****************************************************************************
* Public Types
-
************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************
+/****************************************************************************
* Public Data
-
************************************************************************************/
+ ****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
@@ -104,9 +110,9 @@ extern "C"
#define EXTERN extern
#endif
-/************************************************************************************
- * Public Functions
-
************************************************************************************/
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
#undef EXTERN
#ifdef __cplusplus
diff --git a/arch/arm/include/stm32f7/stm32f72xx73xx_irq.h
b/arch/arm/include/stm32f7/stm32f72xx73xx_irq.h
index ca2c448..4ffc3c6 100644
--- a/arch/arm/include/stm32f7/stm32f72xx73xx_irq.h
+++ b/arch/arm/include/stm32f7/stm32f72xx73xx_irq.h
@@ -1,4 +1,4 @@
-/****************************************************************************************************
+/****************************************************************************
* arch/arm/include/stm32f7/stm32f72xx73xx_irq.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
@@ -33,31 +33,35 @@
* POSSIBILITY OF SUCH DAMAGE.
*
*Change Record:
- * bf20171107 Created file. It's identical to stm32f74xx75xx_irq except for the
- * exclusions noted by this tag, and the addition of the last IRQ
- * for SDMMC2 (IRQ103).
-
****************************************************************************************************/
+ * bf20171107 Created file. It's identical to stm32f74xx75xx_irq except for
+ * the exclusions noted by this tag, and the addition of the
+ * last IRQ for SDMMC2 (IRQ103).
+ ****************************************************************************/
-/* This file should never be included directly but, rather, only indirectly
through arch/irq.h */
+/* This file should never be included directly but, rather, only indirectly
+ * through arch/irq.h
+ */
#ifndef __ARCH_ARM_INCLUDE_STM32F7_STM32F72XX73XX_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32F7_STM32F72XX73XX_IRQ_H
-/****************************************************************************************************
+/****************************************************************************
* Included Files
-
****************************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
-/****************************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
-
****************************************************************************************************/
+ ****************************************************************************/
-/* IRQ numbers. The IRQ number corresponds vector number and hence map
directly to bits in the
- * NVIC. This does, however, waste several words of memory in the IRQ to
handle mapping tables.
+/* IRQ numbers. The IRQ number corresponds vector number and hence map
+ * directly to bits in the NVIC. This does, however, waste several words of
+ * memory in the IRQ to handle mapping tables.
*
- * Processor Exceptions (vectors 0-15). These common definitions can be found
in the file
- * nuttx/arch/arm/include/stm32f7/irq.h which includes this file
+ * Processor Exceptions (vectors 0-15). These common definitions can be
+ * found in the file nuttx/arch/arm/include/stm32f7/irq.h, which includes
+ * this file.
*
* External interrupts (vectors >= 16)
*/
@@ -166,13 +170,13 @@
#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS)
-/****************************************************************************************************
+/****************************************************************************
* Public Types
-
****************************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************************
+/****************************************************************************
* Public Data
-
****************************************************************************************************/
+ ****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
@@ -183,9 +187,9 @@ extern "C"
#define EXTERN extern
#endif
-/****************************************************************************************************
- * Public Functions
-
****************************************************************************************************/
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
#undef EXTERN
#ifdef __cplusplus
diff --git a/arch/arm/include/stm32f7/stm32f74xx75xx_irq.h
b/arch/arm/include/stm32f7/stm32f74xx75xx_irq.h
index 48e2836..cfa9d66 100644
--- a/arch/arm/include/stm32f7/stm32f74xx75xx_irq.h
+++ b/arch/arm/include/stm32f7/stm32f74xx75xx_irq.h
@@ -1,4 +1,4 @@
-/****************************************************************************************************
+/****************************************************************************
* arch/arm/include/stm32f7/stm32f74xx75xx_irq.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
@@ -31,28 +31,32 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
-
****************************************************************************************************/
+ ****************************************************************************/
-/* This file should never be included directly but, rather, only indirectly
through arch/irq.h */
+/* This file should never be included directly but, rather, only indirectly
+ * through arch/irq.h
+ */
#ifndef __ARCH_ARM_INCLUDE_STM32F7_STM32F74XX75XX_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32F7_STM32F74XX75XX_IRQ_H
-/****************************************************************************************************
+/****************************************************************************
* Included Files
-
****************************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
-/****************************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
-
****************************************************************************************************/
+ ****************************************************************************/
-/* IRQ numbers. The IRQ number corresponds vector number and hence map
directly to bits in the
- * NVIC. This does, however, waste several words of memory in the IRQ to
handle mapping tables.
+/* IRQ numbers. The IRQ number corresponds vector number and hence map
+ * directly to bits in the NVIC. This does, however, waste several words of
+ * memory in the IRQ to handle mapping tables.
*
- * Processor Exceptions (vectors 0-15). These common definitions can be found
in the file
- * nuttx/arch/arm/include/stm32f7/irq.h which includes this file
+ * Processor Exceptions (vectors 0-15). These common definitions can be
+ * found in the file nuttx/arch/arm/include/stm32f7/irq.h, which includes
+ * this file
*
* External interrupts (vectors >= 16)
*/
@@ -171,13 +175,13 @@
#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS)
-/****************************************************************************************************
+/****************************************************************************
* Public Types
-
****************************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************************
+/****************************************************************************
* Public Data
-
****************************************************************************************************/
+ ****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
@@ -188,9 +192,9 @@ extern "C"
#define EXTERN extern
#endif
-/****************************************************************************************************
- * Public Functions
-
****************************************************************************************************/
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
#undef EXTERN
#ifdef __cplusplus
diff --git a/arch/arm/include/stm32f7/stm32f76xx77xx_irq.h
b/arch/arm/include/stm32f7/stm32f76xx77xx_irq.h
index 4b3630e..f5d1e46 100644
--- a/arch/arm/include/stm32f7/stm32f76xx77xx_irq.h
+++ b/arch/arm/include/stm32f7/stm32f76xx77xx_irq.h
@@ -1,4 +1,4 @@
-/****************************************************************************************************
+/****************************************************************************
* arch/arm/include/stm32f7/stm32f76xx77xx_irq.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
@@ -32,141 +32,145 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
-
****************************************************************************************************/
+ ****************************************************************************/
-/* This file should never be included directly but, rather, only indirectly
through arch/irq.h */
+/* This file should never be included directly but, rather, only indirectly
+ * through arch/irq.h
+ */
#ifndef __ARCH_ARM_INCLUDE_STM32F7_STM32F76XX77XX_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32F7_STM32F76XX77XX_IRQ_H
-/****************************************************************************************************
+/****************************************************************************
* Included Files
-
****************************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
-/****************************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
-
****************************************************************************************************/
+ ****************************************************************************/
-/* IRQ numbers. The IRQ number corresponds vector number and hence map
directly to bits in the
- * NVIC. This does, however, waste several words of memory in the IRQ to
handle mapping tables.
+/* IRQ numbers. The IRQ number corresponds vector number and hence map
+ * directly to bits in the NVIC. This does, however, waste several words of
+ * memory in the IRQ to handle mapping tables.
*
- * Processor Exceptions (vectors 0-15). These common definitions can be found
in the file
- * nuttx/arch/arm/include/stm32f7/irq.h which includes this file
+ * Processor Exceptions (vectors 0-15). These common definitions can be
+ * found in the file nuttx/arch/arm/include/stm32f7/irq.h which includes
+ * this file
*
* External interrupts (vectors >= 16)
*/
-#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog
interrupt */
-#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI
Line detection interrupt */
-#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper and time
stamp interrupts */
-#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Tamper and time
stamp interrupts */
-#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global
interrupt */
-#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global
interrupt */
-#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global
interrupt */
-#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0
interrupt */
-#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1
interrupt */
-#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2
interrupt */
-#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3
interrupt */
-#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4
interrupt */
-#define STM32_IRQ_DMA1S0 (STM32_IRQ_FIRST + 11) /* 11: DMA1 Stream 0
global interrupt */
-#define STM32_IRQ_DMA1S1 (STM32_IRQ_FIRST + 12) /* 12: DMA1 Stream 1
global interrupt */
-#define STM32_IRQ_DMA1S2 (STM32_IRQ_FIRST + 13) /* 13: DMA1 Stream 2
global interrupt */
-#define STM32_IRQ_DMA1S3 (STM32_IRQ_FIRST + 14) /* 14: DMA1 Stream 3
global interrupt */
-#define STM32_IRQ_DMA1S4 (STM32_IRQ_FIRST + 15) /* 15: DMA1 Stream 4
global interrupt */
-#define STM32_IRQ_DMA1S5 (STM32_IRQ_FIRST + 16) /* 16: DMA1 Stream 5
global interrupt */
-#define STM32_IRQ_DMA1S6 (STM32_IRQ_FIRST + 17) /* 17: DMA1 Stream 6
global interrupt */
-#define STM32_IRQ_ADC (STM32_IRQ_FIRST + 18) /* 18: ADC1, ADC2, and
ADC3 global interrupt */
-#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts
*/
-#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST + 20) /* 20: CAN1 RX0
interrupts */
-#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt
*/
-#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt
*/
-#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5]
interrupts */
-#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break
interrupt */
-#define STM32_IRQ_TIM9 (STM32_IRQ_FIRST + 24) /* 24: TIM9 global
interrupt */
-#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update
interrupt */
-#define STM32_IRQ_TIM10 (STM32_IRQ_FIRST + 25) /* 25: TIM10 global
interrupt */
-#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger and
Commutation interrupts */
-#define STM32_IRQ_TIM11 (STM32_IRQ_FIRST + 26) /* 26: TIM11 global
interrupt */
-#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture
Compare interrupt */
-#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global
interrupt */
-#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global
interrupt */
-#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global
interrupt */
-#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event
interrupt */
-#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error
interrupt */
-#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event
interrupt */
-#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error
interrupt */
-#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global
interrupt */
-#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global
interrupt */
-#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global
interrupt */
-#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global
interrupt */
-#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global
interrupt */
-#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10]
interrupts */
-#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through
EXTI line interrupt */
-#define STM32_IRQ_OTGFSWKUP (STM32_IRQ_FIRST + 42) /* 42: USB On-The-Go FS
Wakeup through EXTI line interrupt */
-#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 43) /* 43: TIM8 Break
interrupt */
-#define STM32_IRQ_TIM12 (STM32_IRQ_FIRST + 43) /* 43: TIM12 global
interrupt */
-#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 44) /* 44: TIM8 Update
interrupt */
-#define STM32_IRQ_TIM13 (STM32_IRQ_FIRST + 44) /* 44: TIM13 global
interrupt */
-#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 45) /* 45: TIM8 Trigger and
Commutation interrupts */
-#define STM32_IRQ_TIM14 (STM32_IRQ_FIRST + 45) /* 45: TIM14 global
interrupt */
-#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 46) /* 46: TIM8 Capture
Compare interrupt */
-#define STM32_IRQ_DMA1S7 (STM32_IRQ_FIRST + 47) /* 47: DMA1 Stream 7
global interrupt */
-#define STM32_IRQ_FMC (STM32_IRQ_FIRST + 48) /* 48: FMC global
interrupt */
-#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST + 49) /* 49: SDMMC1 global
interrupt */
-#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 50) /* 50: TIM5 global
interrupt */
-#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 51) /* 51: SPI3 global
interrupt */
-#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 52) /* 52: UART4 global
interrupt */
-#define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 53) /* 53: UART5 global
interrupt */
-#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 54) /* 54: TIM6 global
interrupt */
-#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 54) /* 54: DAC1 and DAC2
underrun error interrupts */
-#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 55) /* 55: TIM7 global
interrupt */
-#define STM32_IRQ_DMA2S0 (STM32_IRQ_FIRST + 56) /* 56: DMA2 Stream 0
global interrupt */
-#define STM32_IRQ_DMA2S1 (STM32_IRQ_FIRST + 57) /* 57: DMA2 Stream 1
global interrupt */
-#define STM32_IRQ_DMA2S2 (STM32_IRQ_FIRST + 58) /* 58: DMA2 Stream 2
global interrupt */
-#define STM32_IRQ_DMA2S3 (STM32_IRQ_FIRST + 59) /* 59: DMA2 Stream 3
global interrupt */
-#define STM32_IRQ_DMA2S4 (STM32_IRQ_FIRST + 60) /* 60: DMA2 Stream 4
global interrupt */
-#define STM32_IRQ_ETH (STM32_IRQ_FIRST + 61) /* 61: Ethernet global
interrupt */
-#define STM32_IRQ_ETHWKUP (STM32_IRQ_FIRST + 62) /* 62: Ethernet Wakeup
through EXTI line interrupt */
-#define STM32_IRQ_CAN2TX (STM32_IRQ_FIRST + 63) /* 63: CAN2 TX interrupts
*/
-#define STM32_IRQ_CAN2RX0 (STM32_IRQ_FIRST + 64) /* 64: CAN2 RX0
interrupts */
-#define STM32_IRQ_CAN2RX1 (STM32_IRQ_FIRST + 65) /* 65: CAN2 RX1 interrupt
*/
-#define STM32_IRQ_CAN2SCE (STM32_IRQ_FIRST + 66) /* 66: CAN2 SCE interrupt
*/
-#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST + 67) /* 67: USB On The Go FS
global interrupt */
-#define STM32_IRQ_DMA2S5 (STM32_IRQ_FIRST + 68) /* 68: DMA2 Stream 5
global interrupt */
-#define STM32_IRQ_DMA2S6 (STM32_IRQ_FIRST + 69) /* 69: DMA2 Stream 6
global interrupt */
-#define STM32_IRQ_DMA2S7 (STM32_IRQ_FIRST + 70) /* 70: DMA2 Stream 7
global interrupt */
-#define STM32_IRQ_USART6 (STM32_IRQ_FIRST + 71) /* 71: USART6 global
interrupt */
-#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 72) /* 72: I2C3 event
interrupt */
-#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 73) /* 73: I2C3 error
interrupt */
-#define STM32_IRQ_OTGHSEP1OUT (STM32_IRQ_FIRST + 74) /* 74: USB On The Go HS
End Point 1 Out global interrupt */
-#define STM32_IRQ_OTGHSEP1IN (STM32_IRQ_FIRST + 75) /* 75: USB On The Go HS
End Point 1 In global interrupt */
-#define STM32_IRQ_OTGHSWKUP (STM32_IRQ_FIRST + 76) /* 76: USB On The Go HS
Wakeup through EXTI interrupt */
-#define STM32_IRQ_OTGHS (STM32_IRQ_FIRST + 77) /* 77: USB On The Go HS
global interrupt */
-#define STM32_IRQ_DCMI (STM32_IRQ_FIRST + 78) /* 78: DCMI global
interrupt */
-#define STM32_IRQ_CRYP (STM32_IRQ_FIRST + 79) /* 79: CRYP crypto global
interrupt */
-#define STM32_IRQ_HASH (STM32_IRQ_FIRST + 80) /* 80: Hash and Rng
global interrupt */
-#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 80) /* 80: Hash and Rng
global interrupt */
-#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 81) /* 81: FPU global
interrupt */
-#define STM32_IRQ_UART7 (STM32_IRQ_FIRST + 82) /* 82: UART7 global
interrupt */
-#define STM32_IRQ_UART8 (STM32_IRQ_FIRST + 83) /* 83: UART8 global
interrupt */
-#define STM32_IRQ_SPI4 (STM32_IRQ_FIRST + 84) /* 84: SPI4 global
interrupt */
-#define STM32_IRQ_SPI5 (STM32_IRQ_FIRST + 85) /* 85: SPI5 global
interrupt */
-#define STM32_IRQ_SPI6 (STM32_IRQ_FIRST + 86) /* 86: SPI6 global
interrupt */
-#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 87) /* 87: SAI1 global
interrupt */
-#define STM32_IRQ_LTDCINT (STM32_IRQ_FIRST + 88) /* 88: LCD-TFT global
interrupt */
-#define STM32_IRQ_LTDCERRINT (STM32_IRQ_FIRST + 89) /* 89: LCD-TFT global
Error interrupt */
-#define STM32_IRQ_DMA2D (STM32_IRQ_FIRST + 90) /* 90: DMA2D global
interrupt */
-#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST + 91) /* 91: SAI2 global
interrupt */
-#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST + 92) /* 92: QuadSPI global
interrupt */
-#define STM32_IRQ_LPTIMER1 (STM32_IRQ_FIRST + 93) /* 93: LP Timer1 global
interrupt */
-#define STM32_IRQ_HDMICEC (STM32_IRQ_FIRST + 94) /* 94: HDMI-CEC global
interrupt */
-#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST + 95) /* 95: I2C4 event
interrupt */
-#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST + 96) /* 96: I2C4 Error
interrupt */
-#define STM32_IRQ_SPDIFRX (STM32_IRQ_FIRST + 97) /* 97: SPDIFRX global
interrupt */
-#define STM32_IRQ_DSIHOST (STM32_IRQ_FIRST + 98) /* 98: DSI host global
interrupt */
-#define STM32_IRQ_DFSDM1FLT0 (STM32_IRQ_FIRST + 99) /* 99: DFSDM1 Filter 0
global interrupt */
+#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog
interrupt */
+#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI
Line detection interrupt */
+#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper and time
stamp interrupts */
+#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Tamper and time
stamp interrupts */
+#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global
interrupt */
+#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global
interrupt */
+#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global
interrupt */
+#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0
interrupt */
+#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1
interrupt */
+#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2
interrupt */
+#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3
interrupt */
+#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4
interrupt */
+#define STM32_IRQ_DMA1S0 (STM32_IRQ_FIRST + 11) /* 11: DMA1 Stream 0
global interrupt */
+#define STM32_IRQ_DMA1S1 (STM32_IRQ_FIRST + 12) /* 12: DMA1 Stream 1
global interrupt */
+#define STM32_IRQ_DMA1S2 (STM32_IRQ_FIRST + 13) /* 13: DMA1 Stream 2
global interrupt */
+#define STM32_IRQ_DMA1S3 (STM32_IRQ_FIRST + 14) /* 14: DMA1 Stream 3
global interrupt */
+#define STM32_IRQ_DMA1S4 (STM32_IRQ_FIRST + 15) /* 15: DMA1 Stream 4
global interrupt */
+#define STM32_IRQ_DMA1S5 (STM32_IRQ_FIRST + 16) /* 16: DMA1 Stream 5
global interrupt */
+#define STM32_IRQ_DMA1S6 (STM32_IRQ_FIRST + 17) /* 17: DMA1 Stream 6
global interrupt */
+#define STM32_IRQ_ADC (STM32_IRQ_FIRST + 18) /* 18: ADC1, ADC2, and
ADC3 global interrupt */
+#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST + 19) /* 19: CAN1 TX
interrupts */
+#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST + 20) /* 20: CAN1 RX0
interrupts */
+#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST + 21) /* 21: CAN1 RX1
interrupt */
+#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST + 22) /* 22: CAN1 SCE
interrupt */
+#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5]
interrupts */
+#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break
interrupt */
+#define STM32_IRQ_TIM9 (STM32_IRQ_FIRST + 24) /* 24: TIM9 global
interrupt */
+#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update
interrupt */
+#define STM32_IRQ_TIM10 (STM32_IRQ_FIRST + 25) /* 25: TIM10 global
interrupt */
+#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger and
Commutation interrupts */
+#define STM32_IRQ_TIM11 (STM32_IRQ_FIRST + 26) /* 26: TIM11 global
interrupt */
+#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture
Compare interrupt */
+#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global
interrupt */
+#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global
interrupt */
+#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global
interrupt */
+#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event
interrupt */
+#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error
interrupt */
+#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event
interrupt */
+#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error
interrupt */
+#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global
interrupt */
+#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global
interrupt */
+#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global
interrupt */
+#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global
interrupt */
+#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global
interrupt */
+#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10]
interrupts */
+#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm
through EXTI line interrupt */
+#define STM32_IRQ_OTGFSWKUP (STM32_IRQ_FIRST + 42) /* 42: USB On-The-Go FS
Wakeup through EXTI line interrupt */
+#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 43) /* 43: TIM8 Break
interrupt */
+#define STM32_IRQ_TIM12 (STM32_IRQ_FIRST + 43) /* 43: TIM12 global
interrupt */
+#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 44) /* 44: TIM8 Update
interrupt */
+#define STM32_IRQ_TIM13 (STM32_IRQ_FIRST + 44) /* 44: TIM13 global
interrupt */
+#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 45) /* 45: TIM8 Trigger and
Commutation interrupts */
+#define STM32_IRQ_TIM14 (STM32_IRQ_FIRST + 45) /* 45: TIM14 global
interrupt */
+#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 46) /* 46: TIM8 Capture
Compare interrupt */
+#define STM32_IRQ_DMA1S7 (STM32_IRQ_FIRST + 47) /* 47: DMA1 Stream 7
global interrupt */
+#define STM32_IRQ_FMC (STM32_IRQ_FIRST + 48) /* 48: FMC global
interrupt */
+#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST + 49) /* 49: SDMMC1 global
interrupt */
+#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 50) /* 50: TIM5 global
interrupt */
+#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 51) /* 51: SPI3 global
interrupt */
+#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 52) /* 52: UART4 global
interrupt */
+#define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 53) /* 53: UART5 global
interrupt */
+#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 54) /* 54: TIM6 global
interrupt */
+#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 54) /* 54: DAC1 and DAC2
underrun error interrupts */
+#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 55) /* 55: TIM7 global
interrupt */
+#define STM32_IRQ_DMA2S0 (STM32_IRQ_FIRST + 56) /* 56: DMA2 Stream 0
global interrupt */
+#define STM32_IRQ_DMA2S1 (STM32_IRQ_FIRST + 57) /* 57: DMA2 Stream 1
global interrupt */
+#define STM32_IRQ_DMA2S2 (STM32_IRQ_FIRST + 58) /* 58: DMA2 Stream 2
global interrupt */
+#define STM32_IRQ_DMA2S3 (STM32_IRQ_FIRST + 59) /* 59: DMA2 Stream 3
global interrupt */
+#define STM32_IRQ_DMA2S4 (STM32_IRQ_FIRST + 60) /* 60: DMA2 Stream 4
global interrupt */
+#define STM32_IRQ_ETH (STM32_IRQ_FIRST + 61) /* 61: Ethernet global
interrupt */
+#define STM32_IRQ_ETHWKUP (STM32_IRQ_FIRST + 62) /* 62: Ethernet Wakeup
through EXTI line interrupt */
+#define STM32_IRQ_CAN2TX (STM32_IRQ_FIRST + 63) /* 63: CAN2 TX
interrupts */
+#define STM32_IRQ_CAN2RX0 (STM32_IRQ_FIRST + 64) /* 64: CAN2 RX0
interrupts */
+#define STM32_IRQ_CAN2RX1 (STM32_IRQ_FIRST + 65) /* 65: CAN2 RX1
interrupt */
+#define STM32_IRQ_CAN2SCE (STM32_IRQ_FIRST + 66) /* 66: CAN2 SCE
interrupt */
+#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST + 67) /* 67: USB On The Go FS
global interrupt */
+#define STM32_IRQ_DMA2S5 (STM32_IRQ_FIRST + 68) /* 68: DMA2 Stream 5
global interrupt */
+#define STM32_IRQ_DMA2S6 (STM32_IRQ_FIRST + 69) /* 69: DMA2 Stream 6
global interrupt */
+#define STM32_IRQ_DMA2S7 (STM32_IRQ_FIRST + 70) /* 70: DMA2 Stream 7
global interrupt */
+#define STM32_IRQ_USART6 (STM32_IRQ_FIRST + 71) /* 71: USART6 global
interrupt */
+#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 72) /* 72: I2C3 event
interrupt */
+#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 73) /* 73: I2C3 error
interrupt */
+#define STM32_IRQ_OTGHSEP1OUT (STM32_IRQ_FIRST + 74) /* 74: USB On The Go HS
End Point 1 Out global interrupt */
+#define STM32_IRQ_OTGHSEP1IN (STM32_IRQ_FIRST + 75) /* 75: USB On The Go HS
End Point 1 In global interrupt */
+#define STM32_IRQ_OTGHSWKUP (STM32_IRQ_FIRST + 76) /* 76: USB On The Go HS
Wakeup through EXTI interrupt */
+#define STM32_IRQ_OTGHS (STM32_IRQ_FIRST + 77) /* 77: USB On The Go HS
global interrupt */
+#define STM32_IRQ_DCMI (STM32_IRQ_FIRST + 78) /* 78: DCMI global
interrupt */
+#define STM32_IRQ_CRYP (STM32_IRQ_FIRST + 79) /* 79: CRYP crypto
global interrupt */
+#define STM32_IRQ_HASH (STM32_IRQ_FIRST + 80) /* 80: Hash and Rng
global interrupt */
+#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 80) /* 80: Hash and Rng
global interrupt */
+#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 81) /* 81: FPU global
interrupt */
+#define STM32_IRQ_UART7 (STM32_IRQ_FIRST + 82) /* 82: UART7 global
interrupt */
+#define STM32_IRQ_UART8 (STM32_IRQ_FIRST + 83) /* 83: UART8 global
interrupt */
+#define STM32_IRQ_SPI4 (STM32_IRQ_FIRST + 84) /* 84: SPI4 global
interrupt */
+#define STM32_IRQ_SPI5 (STM32_IRQ_FIRST + 85) /* 85: SPI5 global
interrupt */
+#define STM32_IRQ_SPI6 (STM32_IRQ_FIRST + 86) /* 86: SPI6 global
interrupt */
+#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 87) /* 87: SAI1 global
interrupt */
+#define STM32_IRQ_LTDCINT (STM32_IRQ_FIRST + 88) /* 88: LCD-TFT global
interrupt */
+#define STM32_IRQ_LTDCERRINT (STM32_IRQ_FIRST + 89) /* 89: LCD-TFT global
Error interrupt */
+#define STM32_IRQ_DMA2D (STM32_IRQ_FIRST + 90) /* 90: DMA2D global
interrupt */
+#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST + 91) /* 91: SAI2 global
interrupt */
+#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST + 92) /* 92: QuadSPI global
interrupt */
+#define STM32_IRQ_LPTIMER1 (STM32_IRQ_FIRST + 93) /* 93: LP Timer1 global
interrupt */
+#define STM32_IRQ_HDMICEC (STM32_IRQ_FIRST + 94) /* 94: HDMI-CEC global
interrupt */
+#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST + 95) /* 95: I2C4 event
interrupt */
+#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST + 96) /* 96: I2C4 Error
interrupt */
+#define STM32_IRQ_SPDIFRX (STM32_IRQ_FIRST + 97) /* 97: SPDIFRX global
interrupt */
+#define STM32_IRQ_DSIHOST (STM32_IRQ_FIRST + 98) /* 98: DSI host global
interrupt */
+#define STM32_IRQ_DFSDM1FLT0 (STM32_IRQ_FIRST + 99) /* 99: DFSDM1 Filter 0
global interrupt */
#define STM32_IRQ_DFSDM1FLT1 (STM32_IRQ_FIRST + 100) /* 100: DFSDM1 Filter 1
global interrupt */
#define STM32_IRQ_DFSDM1FLT2 (STM32_IRQ_FIRST + 101) /* 101: DFSDM1 Filter 2
global interrupt */
#define STM32_IRQ_DFSDM1FLT3 (STM32_IRQ_FIRST + 102) /* 102: DFSDM1 Filter 3
global interrupt */
@@ -184,13 +188,13 @@
#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS)
-/****************************************************************************************************
+/****************************************************************************
* Public Types
-
****************************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************************
+/****************************************************************************
* Public Data
-
****************************************************************************************************/
+ ****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
@@ -201,9 +205,9 @@ extern "C"
#define EXTERN extern
#endif
-/****************************************************************************************************
- * Public Functions
-
****************************************************************************************************/
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
#undef EXTERN
#ifdef __cplusplus
