michi-jung commented on a change in pull request #2974: URL: https://github.com/apache/incubator-nuttx/pull/2974#discussion_r594901666
########## File path: arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h ########## @@ -0,0 +1,867 @@ +/**************************************************************************** + * arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L562xx_RCC_H +#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L562xx_RCC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#if defined(CONFIG_STM32L5_STM32L562XX) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32L5_RCC_CR_OFFSET 0x0000 /* Clock control register */ +#define STM32L5_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ +#define STM32L5_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ +#define STM32L5_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ +#define STM32L5_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ +#define STM32L5_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */ +#define STM32L5_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ +#define STM32L5_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ +#define STM32L5_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ +#define STM32L5_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ +#define STM32L5_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ +#define STM32L5_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ +#define STM32L5_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ +#define STM32L5_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ +#define STM32L5_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ +#define STM32L5_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ +#define STM32L5_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ +#define STM32L5_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ +#define STM32L5_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ +#define STM32L5_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ +#define STM32L5_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ +#define STM32L5_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ +#define STM32L5_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ +#define STM32L5_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ +#define STM32L5_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ +#define STM32L5_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ +#define STM32L5_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ +#define STM32L5_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ +#define STM32L5_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ +#define STM32L5_RCC_CSR_OFFSET 0x0094 /* Control/status register */ +#define STM32L5_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ +#define STM32L5_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */ +#define STM32L5_RCC_SECCFGR_OFFSET 0x00b8 /* Secure configuration register */ +#define STM32L5_RCC_SECSR_OFFSET 0x00bc /* Secure status register */ +#define STM32L5_RCC_AHB1SECSR_OFFSET 0x00e8 /* AHB1 security status register */ +#define STM32L5_RCC_AHB2SECSR_OFFSET 0x00ec /* AHB2 security status register */ +#define STM32L5_RCC_AHB3SECSR_OFFSET 0x00f0 /* AHB3 security status register */ +#define STM32L5_RCC_APB1SECSR1_OFFSET 0x00f8 /* APB1 security status register 1 */ +#define STM32L5_RCC_APB1SECSR2_OFFSET 0x00fc /* APB1 security status register 2 */ +#define STM32L5_RCC_APB2SECSR_OFFSET 0x0100 /* APB2 security status register */ + +/* Register Addresses *******************************************************/ + +#define STM32L5_RCC_CR (STM32L5_RCC_BASE+STM32L5_RCC_CR_OFFSET) Review comment: Please have a look at https://github.com/apache/incubator-nuttx/pull/2974/commits/0582434c43ddf642c312b4fc6210d060a151e01f (The same commit applies to your next review finding) ---------------------------------------------------------------- This is an automated message from the Apache Git Service. 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